Applied Materials, Inc.

Ramesh Krishnamurthy

Ajay Kumar

Lakshmanan Karuppiah

Brad Eaton

Alexander N Lerner

James S Papanu

Michael N Grimbergen

Madhavi R Chandrachood

Wenguang Li

Prabhat Kumar

Xiaoyi Chen

Simon W Tam

Jeffrey X Tran

Methods and apparatus for the in-situ measurement of metrology parameters are disclosed herein. Some embodiments of the disclosure further provide for the real-time adjustment of process parameters based on the measure metrology parameters. Some embodiments of the disclosure provide for a multi-stage processing chamber top plate with one or more sensors between process stations.

In-situ metrology and process control

Etch masks and methods of dicing semiconductor wafers are described. In an example, an etch mask for a wafer singulation process includes a water-soluble matrix based on a solid component and water. The etch mask also includes a plurality of particles dispersed throughout the water-soluble matrix. The plurality of particles has an average diameter approximately in the range of 5-100 nanometers. A ratio of weight % of the solid component to weight % of the plurality of particles is approximately in the range of 1:0.1-1:4.

Etch mask for hybrid laser scribing and plasma etch wafer singulation process

A method for etching a chromium layer is provided herein. In one embodiment, a method for etching a chromium layer includes providing a filmstack in an etching chamber, the filmstack having a chromium layer partially exposed through a patterned layer, providing at least one halogen containing process gas to a processing chamber, biasing the layer disposed on a substrate support in the processing chamber with a plurality of power pulses less than 600 Watts, and etching the chromium layer through a patterned mask. The method for plasma etching a chromium layer described herein is particularly suitable for fabricating photomasks.

Method for plasma etching a chromium layer suitable for photomask fabrication

A method and apparatus for process integration in manufacture of a gate structure of a field effect transistor are disclosed. The method includes assembling an integrated substrate processing system having a metrology module and a vacuumed processing platform to perform controlled and adaptive plasma processes without exposing the substrate to a non-vacuumed environment.

Cluster tool and method for process integration in manufacture of a gate structure of a field effect transistor

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Sunnyvale, CA, United States of America

Ramesh Krishnamurthy