Intel Corporation

Ramesh G Illikkal

Ravishankar Iyer

Donald K Newell

Srihari Makineni

Li Zhao

Antonio Gonzalez

Fernando Latorre

Leena K Puthiyedath

Pedro Lopez

Jaume Abella

Jaideep Moses

Ram Huggahalli

Josep M Codina

Jose-Alejandro Pineiro

Enric Gibert

A method, computer readable medium, and system are disclosed. In one embodiment, the method comprises setting a quality of service (QoS) priority level value for one or more computer system platform resources, other than a central processor core, relating to a task running on the computer system, and determining whether the one or more computer system platform resources will be allocated to the task based on the QoS priority level setting.

Quality of service implementation for platform resources

Apparatus and computing systems associated with cache sharing based thread control are described. One embodiment includes a memory to store a thread control instruction and a processor to execute the thread control instruction. The processor is coupled to the memory. The processor includes a first unit to dynamically determine a cache sharing behavior between threads in a multi-threaded computing system and a second unit to dynamically control the composition of a set of threads in the multi-threaded computing system. The composition of the set of threads is based, at least in part, on thread affinity as exhibited by cache-sharing behavior. The thread control instruction controls the operation of the first unit and the second unit.

Cache sharing based thread control

A method and system for striping across multiple cache lines to prevent false sharing. A first descriptor to correspond to a first data block is created. The first descriptor is placed in a descriptor ring according to a striping policy to prevent false sharing of a cache line of the computer system.

Striping across multiple cache lines to prevent false sharing

Growing community of inventors

Portland, OR, United States of America

Ramesh G Illikkal