Dell Products Inc.

Emc IP Holding Company LLC

Ramesh Doddaiah

Owen Martin

Malak Alshawabkeh

Sandeep Chandrashekhara

Mohammed Asher

Arieh Don

Sanjib Mallick

Rong Yu

Earl Medeiros

Kaustubh Sahasrabudhe

Deeder M Aurongzeb

Jaeyoo Jung

Malathi Ramakrishnan

John Krasner

Peng Wu

Michael J Scharland

Jeremy O'Hare

Sweetesh Singh

Anoop Raghunathan

Venkata Ippatapu

Mohammed Asher Vt

Mohammed Aamir Vt

Vinay G Rao

Adnan Sahin

Peng Yin

John Creed

Lixin Pang

Kaustubh S Sahasrabudhe

Shao Hu

Steven John Ivester

Jingtong Liu

Benjamin A F Randolph

Evan Barry

Steve Lathrop

Richard Trabing

Richard Goodwill

Mark Hakstead

Aamir Mohammed Vt

Venkata Khambam

Aamir Mohammed

G Vinay Rao

Bernard A Mulligan, Iii

One or more aspects of the present disclosure relate to dynamic performance optimization in storage arrays using tracelet matrices. In embodiments, one or more input/output (IO) operations are received by a storage array. Code path branches taken by each IO operation across storage array components are recorded in a bitmap matrix. Additionally, the likelihood of different code path branches being taken by each IO operation at a storage device or storage group level is forecasted using each IO operation's corresponding bitmap matrix. Performance bottlenecks corresponding to the one or more IO operations are also identified based on a comparison of each IO operation's bitmap matrix and a forecast of the likelihood of the different code path branches being taken by each IO operation targeting a subject storage device or storage group. Further, storage array resources and configurations are dynamically adjusted to resolve the identified performance bottlenecks.

Dynamic performance optimization in storage arrays

A storage system is configured with pools of processor cores. Each pool corresponds uniquely to one of the supported service levels of the storage system. Processor cores within each pool run at a clock speed that is defined for the service level corresponding to the respective pool. Incoming IOs are enqueued for processing by cores of the pool corresponding to the service level of the storage group containing the storage object that is the target of the IO. Forecast IO demand and corresponding data access latency are computed for each service level. If the forecast latency of a service level includes values outside a compliance range, then cores are promoted to, or demoted from, the corresponding pool so that forecast latency stays within the compliance range, thereby reducing power consumption while promoting service level compliance.

Composable core matrix for service level compliance

A method is provided, comprising: obtaining a current wear metric value that is associated with at least one storage device; obtaining an expected wear metric value that corresponds to the current wear metric value; comparing the current wear metric value to the expected wear metric value; and decreasing a maximum power consumption limit of the storage device from a current level to a first level that is lower than the current level, the maximum power consumption limit of the storage device being decreased in response to detecting that the current wear metric value exceeds the expected wear metric value by a first predetermined amount.

Automated power limit write pacing to control NAND endurance

A method for use in a storage system, comprising: instantiating a plurality of virtual storage devices, each virtual storage device corresponding to a different respective group of physical storage devices; assigning one or more of the plurality of virtual storage devices to a landing zone and assigning the rest of the plurality of virtual storage devices to an idle zone; instantiating a data volume, the data volume including a plurality of portions, each portion being hosted on a different respective one of the plurality of virtual storage devices; receiving an I/O request associated with the data volume, the I/O request being one of a read request or a write request; executing the I/O request.

Green disk array enclosure

A method for use in a storage processor, comprising: generating or updating a cache metadata table that identifies a plurality of cache slots, for each of the plurality of cache slots, the cache metadata table including a different respective location identifier that indicates a location for that cache slot; receiving an I/O request that is associated with a logical block address; allocating a given one of the plurality of cache slots to the logical block address based on the respective location identifier that corresponds to the given cache slot; and executing the I/O request by using the given cache slot, wherein using the given cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command based on the memory address.

Location-based global cache tiering

One or more aspects of the present disclosure relate to cache layout optimization. In embodiments, an input/output (IO) workload is received by a storage array. Further, cache slot allocations are dynamically adjusted for each cache segment of global memory based on one or more characteristics of the IO workload.

Cache layout optimization

Aspects of the present disclosure relate to tuning resource allocations based on a storage array feature's impact on the array's global performance. In embodiments, one or more input/output (IO) features used by a storage array to process one or more IO workloads are determined. Additionally, each IO feature's impact for processing the IO workload within a threshold performance requirement can be determined. Further, at least one IO feature's resource allocation can be tuned based on its IO workload processing impact.

Storage array resource allocation based on feature sensitivities

For a source device with an activated snapshot, time series-based prediction of source device write IO operations is implemented, on a per-extent basis, to predict a subset of the source device extents that are likely to be hot (receive write IO operations) during an upcoming time window. Snapshot tracks corresponding to tracks of the predicted hot extents are pre-deduplicated, to accelerate write IO operations on the source device. In instances where the time series-based prediction correctly predicts write IO operations on tracks of an extent, and the tracks of the extent of the source device are pre-deduplicated on the snapshot, it is possible to implement the write IO operations as a redirect on write operation, without first replicating the original track of source data for use by the snapshot. Write IO operations on tracks that are not pre-deduplicated are implemented as copy on write operations.

Time series forecasting for pre-deduplication of snapshots

In an active-active replication environment in which sequential read IOs are distributed across storage array ports and replicas, a first read data size controls selection of a different path to a currently targeted replica to distribute sequential reads across storage system ports and a second read data size controls when a different replica is selected to distribute the sequential reads across storage systems. The storage arrays that maintain the replicas are phase-coordinated to pre-fetch only sequential data that will be accessed in the near future from their local replica. For example, a first storage array prefetches sequential data from a first replica in chunks corresponding to the first data size until sequential data corresponding to the second data size has been prefetched, skips sequential addresses corresponding to the second data size, and prefetches sequential data corresponding to the first data size that is next in sequence relative to the skipped sequential addresses.

Enhancing array prefetch for sequential IOs in active-active remote replication

A storage system is configured with pools of processor cores. Each pool corresponds uniquely to one of the supported service levels of the storage system. In a dynamic time series forecast adjustment mode, processor cores within each pool run at a clock speed that is statically defined for the service level corresponding to the respective pool and core affiliations with pools are dynamically adjusted based on modelled data access latency. During a scheduled event, an event guided core matrix profile overrides the time series forecast adjusted core matrix profile. The event guided core matrix profile includes core clock speeds and pool affiliations, thereby enabling rapid reconfiguration.

Customer informed composable core matrix for sustainable service levels

One or more aspects of the present disclosure relate to distributing write destaging amongst a storage array's boards. In embodiments, an input/output (IO) workload is received at a storage array. In addition, a write IO request in the IO workload is directed to a target board of a plurality of boards of the storage array based on one or more performance-related hyperparameters of each board. Further, write data of the write IO request to a storage device is destaged by the target board.

Distributed write destaging

Autonomous power control is provided on a storage system to enable service level maximum response time controls to be achieved, while also minimizing power consumption, by enabling service level minimum response times to be specified and enforced. A workload/CPU clock speed model is created for the storage system correlating a maximum number of IOPS that the storage system can process for different CPU clock speeds for each workload type. A service level agreement specifies a maximum storage system response time. A storage system minimum response time is also specified, that is used to identify a target CPU clock speed for the workload type being provided by a host. The CPU clock speed is lowered to reduce energy consumption by the storage system toward the target CPU clock speed, and storage system performance is monitored to ensure that the storage system complies with the storage system maximum response time.

Autonomous power control based on service level compliance

Host IO write operations on a given storage group are grouped into cycles of a write destage pipeline for the storage group. Host writes are collected during a capture cycle, while host writes from a previous capture cycle are analyzed and destaged during an apply cycle. After the previous apply cycle has completed, a cycle switch occurs and the current capture cycle becomes the new apply cycle. Anomaly detection is implemented before any IO write operations are destaged during the apply cycle, and if an anomaly is detected the write destage is stopped. The entire apply cycle is either destaged to disk, or is discarded, depending on whether the anomaly is confirmed. By maintaining the order of writes across different cycles, which act as consistency points, it is possible to implement ransomware protection in real time on host write operations, while using ordered write destage to maintain data consistency.

Data protection by delayed ordered write destage operations

A shared global memory segmentation conversion process optimizes conversion of shared Global Memory (GM) in connection with changes to a global memory segmentation policy. When a policy region is to be reduced in size, the GM banks of the policy region are ranked and one or more of the lowest performing GM banks in the policy region are selected to be moved to the other policy region. Similarly, within each policy region, IO pools, used to create slots of particular sizes, that are being reduced in size are determined, and the GM banks of the IO pools are ranked. One or more of the lowest performing GM banks are selected and moved to an IO pool that is being increased in size. This process iterates, re-ranking the remaining GM banks in the policy region/IO pools, until the correct allocation of GM policy regions and IO pools is achieved.

Global memory segmentation conversion

Metadata page prefetch processing for incoming IO operations is provided to increase storage system performance by reducing the frequency of metadata page miss events during IO processing. When an IO is received at a storage system, the IO is placed in an IO queue to be scheduled for processing by an IO processing thread. A metadata page prefetch thread reads the LBA address of the IO and determines whether all of the metadata page(s) that will be needed by the IO processing thread are contained in IO thread metadata resources. In response to a determination that one or more of the required metadata pages are not contained in IO thread metadata resources, the metadata page prefetch thread instructs a MDP thread to move the required metadata page(s) from metadata storage to IO thread metadata resources. The IO processing thread then implements the IO operation using the prefetched metadata.

Growing community of inventors

Westborough, MA, United States of America

Ramesh Doddaiah