International Business Machines Corporation

Ramesh Chandra Agarwal

Fred Gehrung Gustavson

Brett Olsson

Mark A Johnson

Randall Dean Groves

Charu Chandra Aggarwal

Sriram Kolinjivadi Padmanabhan

James Bergheim Shearer

V V V Prasad

Bruce Martin Fleischer

Bishwaranjan Bhattacharjee

Matthew Albert Huras

Min Wang

Timothy Ray Malkemus

Lipyeow Lim

Terry L Lyon

Andrew Augustus Bjorksten

Leslie Anne Cranston

John Joseph Forrest

Tony Wen Hsun Lai

Mahesh V Joshi

Freg G Gustavson

A differential compression method and computer program product combines hash value techniques and suffix array techniques. The invention finds the best matches for every offset of the version file, with respect to a certain granularity and above a certain length threshold. The invention has two variations depending on block size choice. If the block size is kept fixed, the compression performance of the invention is similar to that of the greedy algorithm, without the expensive space and time requirements. If the block size is varied linearly with the reference file size, the invention can run in linear-time and constant-space. It has been shown empirically that the invention performs better than certain known differential compression algorithms in terms of compression and speed.

Method for finding the longest common subsequences between files with applications to differential compression

A repository index records the position of document entries relative to landmark entries within the document. Landmark entries are selecting using a landmarking policy and their position relative to the document are stored in a landmark directory. During index updates, an edit transcript is generated describing the difference between old and new document versions, and both the document repository index and the landmark directory are updated as needed. Thus, the number of update operations preformed as compared with conventional indexing techniques may be substantially reduced when small, localized changes are made to the document. This is due to fact that the positions of document entries are recorded relative to the landmark entries rather than the document itself. By doing so, the document index becomes more shift-invariant, requiring fewer update operations when entries are added or inserted in localized areas of the document.

Dynamic maintenance of web indices using landmarks

Multidimensional clustered tables are provided for efficient processing and management in a relational database management system. A multidimensional clustered table is one whose data is simultaneously clustered along one or more independent dimensions, or clustering keys, and physically organized into blocks or pages on disk. When such a table is created, one can specify one or more keys as dimensions along which to cluster the table's data. Each of the dimensions can consist of one or more columns. Further provided are efficient query processing and maintenance techniques for use in conjunction with multidimensional clustered tables.

Multidimensional data clustering scheme for query processing and maintenance in relational databases

A method for learning signatures of a target class using a sequential covering phased rule-induction. The method balances recall and precision for the target class. A first phase aims for high recall by inducing rules with high support and a reasonable level of accuracy. A second phase improves the precision by learning rules to remove false positives in the collection of the records covered by the first phase rules, while keeping the overall recall at a desirable level. The method constructs a mechanism to assign prediction probability scores to each classification decision. The model includes a set of positive rules that predict presence of the target class, a set of negative rules that predict absence of the target class, and a set of prediction score values corresponding to each pair-wise combination of positive and negative rules. The two-phase method is extensible to a multiphase approach.

Method for building classifier models for event classes via phased rule induction

A system and method for generating itemset associations in a memory storage system comprising many transactions, with each transaction including one or more items capable of forming the itemset associations. The method involves generating a lexicographic tree structure having nodes representing itemset associations meeting a minimum support criteria. In a recursive manner, for each lexicographic least itemset (node) P of the lexicographic tree structure, candidate extensions of the node P are first determined. Then, the support of each of the candidate extensions is counted to determine frequent extension itemsets of that node P, while those itemsets not meeting a predetermined support criteria are eliminated. Child nodes corresponding to the frequent extensions and meeting the predetermined support criteria are created. For each frequent child of node P, all itemset associations for all descendants of node P are generated first. Thus, the lexicographic tree structure is generated in a depth first manner. By projecting transactions upon the lexicographic tree structure in a depth-first manner, the CPU time for counting large itemsets is substantially reduced.

Depth first method for generating itemsets

A method for automatically generating associations of items included in a database. A user first specifies a support criteria indicating a strength of desired associations of items contained in the said database. Then, a recursive program is executed for generating a hierarchical tree structure comprising one or more levels of database itemsets, with each itemset representing item associations determined to have satisfied the specified support criteria. The recursive program includes steps of: characterizing nodes of the tree structure as being either active and enabling generation of new nodes at a new level of the tree, or inactive, at any given time; enabling traversal of the tree structure in a predetermined manner and projecting each of the transactions included in the database onto currently active nodes of the tree structure to generate projected transaction results; and, counting the projected transaction results of the projected transactions at the active nodes to determine whether the further itemsets satisfy the specified support criteria. All itemsets meeting the specified support criteria are added to the tree structure at a new level.

System and method of generating associations

In a data processing unit, an instruction is loaded. Such an instruction includes an operation code field for storing an operation code and at least one operand field, where the operand field includes an indirect addressing mode indicator for indicating enablement of an indirect addressing mode. If an indirect addressing mode is enabled, a general purpose register address is selected from an address field in an indirect register. Finally, the data processing unit addresses a selected one of the plurality of general purpose registers utilizing the general purpose register address during the execution of the operation code by the data processing unit.

Method and system for addressing registers in a data processing unit in

A vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern. Thereafter, the elements are transferred, in a first order, from the input storage area into a vector register interface unit. From the vector register interface unit, the elements are transferred to an output storage area and stored in addressable locations in one of a plurality of preselected patterns. The input storage area may be implemented with cache memory or a register array. The output storage area may be implemented with a cache memory or a register array. The first pattern in the input storage area may include alternating real and imaginary elements. The plurality of preselected patterns may include a reversed order pattern, or a separation of real and imaginary elements into two vector registers.

Method and system in a data processing system for loading and storing

In a data processing unit having a plurality of general purpose registers, an instruction is loaded. Such an instruction includes an operation, and at least one operand field, where the operand field specifies one of a plurality of base registers and a displacement value. To calculate a general purpose register address specified by such an operand field, the displacement value is added to a base value stored in a base register that is specified by a portion of the operand field. Finally, the data processing unit addresses a selected one of the general purpose registers, utilizing the calculated general purpose register address, for execution of the specified operation. Thus, the data processing unit is capable of addressing a larger number of general purpose registers than may be directly addressed utilizing a value represented by a limited number of bits within the operand field.

A matrix processing unit is described which permits high speed numerical computation. The processing unit is a vector processing unit which is formed from a plurality of processing elements. The Ith processing unit has a set of N registers within which the Ith elements or words of N vectors of data are stored. Each processing element has an arithmetic unit which is capable of performing arithmetic operations on the N elements in the set of N registers. Each vector of data has K elements. Therefore, there are K processing elements. A vector operation of the matrix processing unit simultaneously performs the same operation on all elements of two vectors or more. A subsequent vector operation can be performed within one machine cycle time after the preceding vector operation.

Numerically intensive computer accelerator

A computer implemented method performed by a processor having multiple functional units avoids branches in decision support codes by doing arithmetic instructions incorporating condition codes generated by compare instructions. The method comprising the steps of analyzing operations in code to be performed by said processors to identify branch operations, substituting for identified branch operations arithmetic condition codes, decoding and dispatching multiple instructions in one processor cycle, and executing multiple functions in parallel per cycle using each of the functional units of said processor.

Parallel processing method having arithmetical conditions code based

A single-instruction, multiple-data (SIMD) execution unit for use in conjunction with a superscalar data processing system is provided. The SIMD execution unit is coupled to a branch execution unit within a superscalar processor. The branch execution unit fetches instructions from memory and dispatches vector processing instructions to the SIMD execution unit via the instruction bus. The SIMD execution unit includes a control unit and a plurality of processing elements for performing arithmetic operations. The processing elements further include a register file having multiple registers and an arithmetic logic unit coupled to the register file. The arithmetic logic unit may include a fixed-point unit for performing fixed-point vector calculations and a floating-point unit for performing floating-point vector calculations. Once the control unit within the SIMD execution unit receives a vector instruction, the control unit translates the instruction into commands for execution by selected processing elements within the SIMD execution unit. If such a vector instruction requires access to memory, a fixed point execution unit within the superscalar processor may be utilized to calculate a memory address which is then utilized by the SIMD execution unit to access memory.

Method and system for providing a single-instruction, multiple-data

An arithmetic unit keeps a result in carry-save form and uses this form of the result as an input to the next iteration in recurrent computations. The full adder in the recurrent path is eliminated by implementing multiplication by Y(i), where Y(i) is available only in carry-save form. The carry-save arithmetic unit generates a plurality of partial products whose sum is the product AXB, where A is one binary input and B is either a second binary input B' or the sum C'+S' of two binary inputs C' and S'. A selection is made as to whether B is equal to B' or C'+S'. The plurality of partial products and an addition input Z are compressed to two partial products C and S whose sum C+S equals the sum of the plurality of partial products and Z. The partial products C and S are added to produce a binary result X equal to A.times.B+Z. The full adder in the recurrent path is eliminated by a feedback path which returns the partial products C and S to the inputs C' and S' for a next iteration.

Recurrent adrithmetical computation using carry-save arithmetic

A sorting scheme which does not require any compare or branch instructions is particularly useful for computers with multiple parallel functional units. Sorting two numbers or binary strings is performed using arithmetic instructions instead of conventional compare and branch instructions, thereby improving the performance of superscalar and very large instruction word (VLIW) computers. When applied to reduced instruction set computers (RISC), the sorting scheme provides better utilization of floating-point units. The sorting scheme allows floating point representation of data and floating-point instructions to sort binary strings.

Sorting scheme without compare and branch instructions

In a vector processing system for processing vector calculations utilizing a portion of a vector comprising a plurality of elements, means for receiving a vector and a vector processing command are provided. The vector processing system also includes means for receiving and storing a start-element value and an end-element value. An arithmetic logic unit is coupled to the means for receiving the vector, the means for receiving the vector processing command, and the means for receiving the start-element and end-element values. The arithmetic logic unit also includes means for executing the vector processing command utilizing only one or more of the elements in the vector, which are selected by the start-element value and the end-element value.

Growing community of inventors

Yorktown Heights, NY, United States of America

Ramesh Chandra Agarwal