Fairchild Camera and Instrument Corp.

Other

International Business Machines Corporation

Inova Microelectronics Corporation

Ramesh C Varshney

Kalyanasundaram Venkateswaran

Robert J Strain

Paul Wingshing Chung

Gilbert F Amelio

Eugene M Blaser

Wafer level integration is provided by using individually integrated circuits on a wafer substrate and generating an electrically ordered matrix of functional integrated circuits assigned from a random distribution of functional, partially functional, and non-functional circuits. Each circuit is individually tested for functionality and thereafter a conductive grid is formed on said wafer to interconnect all of the circuits on the wafer. Circuits that are tested as being non-functional are isolated prior to formation of the interconnecting grid by eliminating fuses that provide connections between the defective circuit and the conductive grid. Each matrix row includes redundant decoder lines. The redundant decoder lines are programmed to reassign functional circuits from a semiconductor wafer substrate location to a matrix row location in another matrix row having defective circuits. In this way, complete functional matrix rows are formed. Associated input and output lines are assigned in a similar manner to a correct bit position within an input and output byte.

Wafer level integration technique

A disabling circuit 71 responsive to a control signal 81 generated by applying to an IC pin 86 a signal outside the range of normal operating voltages of the device 16. The disabling circuit 71 grounds the output of are dundant address decoder such as 31 to disable a spare element 37 of the device 16, allowing identification of repaired elements.

Redundancy roll call technique

A clock generator circuit for producing with very little power dissipation an output clock signal having levels determined by positive and negative power supply levels from an input clock signal having levels determined by the positive power supply level and ground. In a low state of the input clock signal, an upper or first transistor of an output transistor pair connected in series between positive and negative power supply levels is turned off by applying a ground level to the base thereof, while the lower or second transistor of the output transistor pair is turned off by applying a positive potential to its base. When the input clock signal makes a transition from the low state to the high state, a bootstrap capacitor is charged between the positive and negative power supply levels to provide a boosted positive voltage to turn on the upper transistor. While the bootstrap capacitor is charging, the base of the lower transistor is lightly grounded to partially turn it on. When the charge on the bootstrap capacitor has reached a predetermined level, the base of the first transistor is taken to the negative power supply level through an inverting transistor, the base of which also receives the boosted voltage developed across the bootstrap capacitor. By using a fully dynamic circuit arrangement, only a very small amount of power is required for operating the circuit.

Low power clock generator

A semiconductor memory system is organized into a plurality of segments and is equipped with multiplexed or multifunctional pin for input/output purposes; e.g. the memory address pins, since there is a portion of each memory cycle during which the logic state of the address pins is unimportant. Logic means is provided for coupling the multiplexed pins to the memory segments through the input/output lines upon the occurrence of a test clock signal. The test clock signal is generated during the don't-care portion of the memory cycle.

Test system for segmented memory

An SPS CCD memory using two phase clocking in the serial registers and ripple clocking in the parallel registers with interlacing transfer of charge in the parallel registers to the output serial registers. First alternate parallel registers are coupled to the output register through first transfer gates and first storage gates, and second alternate parallel registers are coupled to the output register through second transfer gates and second storage gates. Third storage gates are provided with each third storage gate alternately receiving charge from a first storage gate and a second storage gate with the third gate delivering the charge to the same storage element of the output register. By linearly staggering the endmost gates of the first alternate parallel registers and the second alternate parallel registers, the interlacing of charge occurs at the endmost gate of the parallel registers.

Serial-parallel-serial charged coupled device memory and a method of

A circuit for providing an identification signal indicative of whether or not an integrated circuit has been repaired includes a circuit which operates at potentials outside the normal range of the integrated circuit. The circuit includes at least one transistor T1 serially connected between a TTL pin 10 of the integrated circuit and a fuse F1. The fuse F1 is also connected to a potential source V.sub.CC. If the integrated circuit is repaired the fuse F1 is opened, and consequently, application of a potential outside the normal range will cause current to flow if fuse F1 has not been opened, and cause no current to flow if fuse F1 has been opened.

Identification of repaired integrated circuits

A programmable address buffer for coupling external addresses to a desired pair of internal memory addresses includes A and B address inputs 11 and 12, a B address output 15 coupled to the B address input 12, a first inverter I30 coupled to the B address input and a B address output, a first switch S2 coupled to switchably connect one of the A and B address inputs 11 and 12 to a node, an A address output coupled to the first node, a second inverter I10 connected to the first node, a third inverter I20 connected between the second node and an A output 14, and a second switch S1 coupled to the second node to switchably connect one of the first node or the second inverter I10 to the second node. In another embodiment an electrical circuit for controlling the addressing of functional sections of a partially functional product includes a first pin 100 coupled by a first fuse F.sub.1 to a first address buffer 150, and a second pin 110 coupled by a second fuse F.sub.5 to a second address buffer 160, a fusible connection F.sub.4 between the second pin 110 and the first buffer 150, and fusible connections F.sub.2, F.sub.3, F.sub.6, and F.sub.7 to each address buffer to connect that address buffer to either of two selected potentials corresponding to the desired state of that buffer.

Programmable address buffer for partial products

A method of providing recessed oxide isolation layers employs prior art techniques to the point at which a photoetched recess has exposed the semiconductor surface in which the recessed oxide isolation layer is to be grown. The semiconductor wafer is then subjected to a nitride layer formation procedure. The nitride layer formed extends into a photoetched recess and forms a nitride layer on the side surfaces of the recess. The newly deposited nitride layer is subjected to an etching process which etches vertically only, exposing the semiconductor surface in a pattern defined by the nitride coated recess. Since the recess walls are lined with a nitride layer, subsequent oxidation growth is restricted to the recess defined by the nitride coated walls. There is no intrusion of the recessed oxide isolation layer into adjacent active areas of the semiconductor material. Thus, the full active width of adjacent areas of the semiconductor is preserved and greater utilization of the available surface area achieved.

Semiconductor structure for recessed isolation oxide

Diagnostic testing of a charge coupled device is facilitated by interconnecting the reference node of the sense amplifier for each data block in the CCD device with a probe contact on the device, thereby eliminating the need for applying a microprobe to the sensitive reference node. Reference voltages under different operating conditions can be evaluated by measuring the device generated reference voltage or by applying variable reference voltages through the probe contact to the reference node.

Method and means for diagnostic testing of CCD memories

A semiconductor digital memory such as a charge coupled device is provided with error detection capability. Error logic responsive to a group of data on the input bus generates a first error code which is stored in memory along with the group of data. When the data is retrieved from memory similar error logic generates a second error code. The first and second error codes are compared, and if the codes are identical the data is assumed to be correct. If codes differ then the data is discarded or errors therein are identified and corrected.

Method and means for internal error check in a digital memory

A sense amplifier for use with a charge coupled device in which capacitive coupled charge is employed with a flip-flop circuit to accelerate sense and readout. Operation of the amplifier is effected with two external clocks and two internally generated clocks.

Sense amplifier for CCD memory

A plurality of charge-coupled device shift registers or shift register elements is used to generate a plurality of packets of charge, each proportional to a different reference potential. Using a sense amplifier or comparator, each of the packets of charge is compared, either simultaneously or sequentially, with one or more packets of charge generated by the potential of an analog signal. Signals from the comparator are then supplied to an encoder or a counter to generate a digital signal representative of the analog signal. In one embodiment the plurality of different reference potentials are generated by positioning the shift registers or shift register elements at various locations along a resistance having a potential applied across it.

Charge-coupled device serial analog-to-digital converter and associated

Method of forming recessed isolation oxide layers

A serial-parallel-serial organized charge-coupled device memory incorporates interlacing and ripple clocking of the parallel shift registers to achieve a high density of bits per unit area. The memory is organized as sixteen 4,096-bit blocks which are randomly accessible. The data in each of the sixteen blocks advance simultaneously at the rate of one bit per cycle. Each block has its own reference charge generator, sense amplifier, input-output decoder and CCD input circuit.

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San Jose, CA, United States of America

Ramesh C Varshney