Apple Inc.

Ramesh Arvapalli

Greg M Hess

Andrew L Arengo

A first plurality of storage cells may be coupled to a first pair of data lines, and a second plurality of storage cells may be coupled to a second pair of data lines. Each storage cell in the first plurality of storage cells may be configured to generate a first output signal on the first pair of data lines in response to an assertion of a respective one of first plurality of selection signals, and each storage cell in the second plurality of storage cells may be configured to generate a second output signal on the second pair of data lines in response to the assertion of a respective one of a second plurality of selection signals. Circuitry may assert a given selection signal from either the first or second plurality of selection signals. An amplifier circuit may amplify either the first or second output signal.

Shared gate fed sense amplifier

A method and various circuit embodiments for low latency initialization of an SRAM are disclosed. In one embodiment, an IC includes an SRAM coupled to at least one functional circuit block. The SRAM includes a number of storage location arranged in rows and columns. The functional circuit block and the SRAM may be in different power domains. Upon initially powering up or a restoration of power, the functional circuit block may assert an initialization signal to begin an initialization process. Responsive to the initialization signal, level shifters may force assertion of various select/enable signals in a decoder associated with the SRAM. Thereafter, initialization data may be written to the SRAM. Writing initialization data may be performed on a row-by-row basis, with all columns in a row being written to substantially simultaneously.

Method and circuits for low latency initialization of static random access memory

An apparatus, system, and method are contemplated in which the apparatus may include a memory with a plurality of pages, circuitry, and a plurality of pre-charge circuits. The circuitry may be configured to receive a first read command and address, corresponding to a given page. The plurality of pre-charge circuits may be configured to charge a plurality of data lines to a predetermined voltage. The circuitry may be configured to read data values from the memory, and transfer the data values to the plurality of data lines. The plurality of pre-charge circuits may be configured to maintain the data on the plurality of data lines. The circuitry may select a first subset of the maintained data, receive a second read command and a second address by the memory, and select a second subset of the maintained data responsive to a determination that the second address corresponds to the given page.

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Santa Clara, CA, United States of America

Ramesh Arvapalli