Qualcomm Incorporated

Ramaprasath Vilangudipitchai

Dorav Kumar

Giby Samson

Lipeng Cao

Seung Hyuk Kang

Venugopal Boynapalli

Divjyot Bhan

Ohsang Kwon

Prayag Bhanubhai Patel

Harshat Pant

Venkat Narayanan

Samrat Sinharoy

Parissa Najdesamii

Rui Chen

Rakesh Vattikonda

Venkatasubramanian Narayanan

De Lu

Kamesh Medisetti

Paras Gupta

Smeeta Heggond

Gaurav Bhargava

Xiangdong Chen

Mohamed Hassan Abu-Rahma

Paul Penzes

Martin Saint-Laurent

Animesh Datta

Seid Hadi Rasouli

Satyanarayana Sahu

Foua Vang

Jeffrey Gemar

Javid Jaffari

Bilal Zafar

Raghavendra Srinivas

Steven James Dillen

Vasisht M Vadi

Jay Madhukar Shah

Mohammed Yousuff Shariff

Mamta Bansal

Keyurkumar Karsanbhai Kansagra

Gudoor Reddy

Peeyush Kumar Parkar

Sachin Bapat

Srivatsan Chellappa

Albert Kumar

Andi Zhao

Xi Luo

Uday Doddannagari

Nitin Partani

Sai Pradeep Kochuri

Anil Kumar Koduru

Uday Shankar Mudigonda

Jitu Khushalbhai Mistry

Arshath Sheeparamatti

A hybrid flop tray, including: a set of flip-flops cascaded along a scan path, wherein a first subset of one or more of the flip-flops of the set includes fin field effect transistors (FinFETs) each sized with a first number of fins, and a second subset of one or more of the flip-flops of the set includes FinFETs each sized with a second number of fins, wherein the first number of fins is different than the second number of fins; and a control circuit configured to provide control signals to the set of flip-flops.

Hybrid flop tray including different fin size flip-flops

At least one integrated power management cell of an IC includes a first cell, which is a 4-height cell, that includes a first continuous n-well, a first power interconnect coupled to a first voltage source associated with a first voltage domain and to the first continuous n-well, a second continuous n-well, a second power interconnect coupled to a second voltage source associated with a second voltage domain and to the second continuous n-well, a first subset of a first voltage level shifter associated with the first voltage domain and coupled to the first power interconnect, and a second subset of the first voltage level shifter associated with the second voltage domain and coupled to the second power interconnect.

Integrated power management cells for gate all around technologies

A system on chip (SOC) comprising: first memory block and a second memory block; a processing unit coupled to the first memory block and the second memory block; a first power multiplexor disposed between the first memory block and the second memory block and coupled to a first power rail configured to provide an operating voltage to both the first memory block and the second memory block; and enable logic circuitry disposed at a periphery of the SOC away from the first memory block and the second memory block, the enable logic being coupled to control terminals of the first power multiplexor.

Systems and methods for adaptive power multiplexing

Certain aspects of the present disclosure are directed to methods and apparatus for configuring a multiply-accumulate (MAC) block in an artificial neural network. A method generally includes receiving, at a neural processing unit comprising one or more logic elements, at least one input associated with a use-case of the neural processing unit; obtaining a set of weights associated with the at least one input; selecting a precision for the set of weights; modifying the set of weights based on the selected precision; and generating an output based, at least in part, on the at least one input, the modified set of weights, and an activation function.

Configurable MAC for neural network applications

A cell on an IC includes a first set of Mlayer interconnects coupled to a first voltage, a second set of Mlayer interconnects coupled to a second voltage different than the first voltage, and a MIM capacitor structure below the Mlayer. The MIM capacitor structure includes a CTM, a CBM, and an insulator between portions of the CTM and the CBM. The first set of Mlayer interconnects is coupled to the CTM. The second set of Mlayer interconnects is coupled to the CBM. The MIM capacitor structure is between the Mlayer and an Mlayer. The MIM capacitor structure includes a plurality of openings. The MIM capacitor structure is continuous within the cell and extends to at least two edges of the cell. In one configuration, the MIM capacitor structure extends to each edge of the cell.

MIMCAP architecture

A system includes: a first power supply; a second power supply; a headswitch disposed between the first power supply and logic circuitry; an enable driver coupling the second power supply to a control terminal of the headswitch; and a voltage generator operable to adjust a control voltage from the second power supply to the control terminal of the headswitch in response to a first voltage level of the first power supply exceeding a reference voltage level.

Systems and methods providing leakage reduction for power gated domains

A level shifter according to some embodiments is disclosed. In some embodiments, a level shifter includes a middle-of-the-line (MOL) capacitor; and a circuit including at least one thin-film transistor coupled to the MOL capacitor, wherein an input voltage provided to the MOL capacitor is split between the MOL capacitor and the circuit. The MOL capacitor can be formed with a contact strip adjacent to a gate structure. A method of forming a level shifter using thin-oxide technologies includes forming a middle-of-the-line (MOL) capacitor; forming a circuit with one or more thin-film transistors; and coupling the MOL capacitor to the circuit such that an input voltage provided at the MOL capacitor is split between the MOL capacitor and the circuit.

High-voltage tolerant level shifter using thin-oxide transistors and a middle-of-the-line (MOL) capacitor

In certain aspects, an apparatus includes a first plurality of power switch devices. Each of the first plurality of power switch devices includes a delay line having a programmable time delay, and a power switch coupled between a supply rail and a circuit block, wherein the power switch has a control input coupled to the delay line. The apparatus also includes a switch manager configured to program the time delays of the delay lines in the first plurality of power switch devices based on a number of active circuit blocks in a system.

Power chain with delay adaptive switches

In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.

Methods and apparatus for using split N-well cells in a merged N-well block

A power multiplexor includes: a first branch including a first transistor coupled in series with a second transistor between a first power supply and a power output; a second branch including a third transistor coupled in series with a fourth transistor between a second power supply and the power output; a controller configured to selectively assert and de-assert a control signal to the first branch and the second branch; a first voltage level shifter coupled between the second transistor and the controller; and a second voltage level shifter coupled between the third transistor and the controller.

Digital power multiplexor

A MOS IC includes pMOS transistors, each having a pMOS transistor drain, source, and gate. Each pMOS transistor gate extends in a first direction and is coupled to other pMOS transistor gates. Each pMOS transistor source/drain are coupled to a first voltage source. The MOS IC further includes a first metal interconnect extending over the pMOS transistors. The first metal interconnect has first and second ends. The first metal interconnect is coupled to each pMOS transistor gate and is coupled to a second voltage source less than the first voltage source. One of each pMOS transistor gate or the second voltage source is coupled to the first metal interconnect through at least one tap point located between the first and second ends. The pMOS transistors and the first metal interconnect function as a decoupling capacitor.

Decoupling capacitor with metal programmable knee frequency

In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.

High speed voltage level shifter

In one embodiment, a voltage level shifter includes a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output. The voltage level shifter also includes a second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.

An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power-multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power-mux tiles perform at least a portion of the power-multiplexing operation.

Adjustable power rail multiplexing

Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.

Voltage comparator

Growing community of inventors

San Diego, CA, United States of America

Ramaprasath Vilangudipitchai