Broadcom Corporation

Other

Sirf Technology, Inc.

Ramanujan K Valmiki

Sandeep Bhatia

Vivian T Hsiun

Sathish Kumar

Chengfuh Jeffrey Tang

Xiaodong Xie

Greg Alan Kranawetter

Francis Cheung

Xuemin Chen

Alexander Garland MacInnis

Marcus Christopher Kellerman

Jason C Demas

Srinivasa Mogathala Prabhakara Reddy

Glen A Grover

Pramod Chandraiah

Benjamin S Giese

Rajugopal Gubbi

Lakshmikanth Pai

Mahadevan Sivagururaman

Girish Raghunath Hulmani

Anand Pande

Aniruddha Sane

Bhaskar Mala Sherigar

Shashank Dabral

Alexander G Macinnis

Sathish Kumar Radhakrishnan

Syed Mohammed Ali

Javaji Sunil Babu

Vidya Praveen

Bhaskar Sherigar

Girish Raghunath Humlani

K Naresh Chandra Srinivas

Ashok Halambi

Madhuri Mandava

Marimuthu Kumar

Bill Safelski

Naresh Chandra Srinivas Koppineedi

Ravindra Bindus

Seru Srinivas

Soorgoli Ashok Halambi

Sarang Ramchandra Shelke

Bhramar Bhushan Vatsa

Dibyapran Sanyal

Nishant Manohar Nakate

Sai Pramod Kumar Atmakuru

William C Salefski

Error concealment for motion picture expert group (MPEG) decoding with personal video recording functionality. Error concealment of MPEG data may take place within various components within playback, recording, reading and writing data systems. The error concealment may be provided within existing systems whose components may not be capable of accommodating errors within MPEG data. In certain embodiments, the available data that contain no errors is maximized to conceal those portions of the data that do include errors.

Error concealment for MPEG decoding with personal video recording functionality

Error concealment for motion picture expert group (MPEG) decoding with personal video recording functionality. Error concealment of MPEG data may take place within various components within playback, recording, reading and writing data systems. The error concealment may be provided within existing systems whose components may not be capable of accommodating errors within MPEG data. In certain embodiments, the available data that contain no errors is maximized to conceal those portions of the data that do include errors. Various layers may be accommodated while performing error concealment, including the MPEG transport stream layer, the video layer, and the audio layer.

Systems, devices, and methods for error detection and correction in digital communication are disclosed. One such method comprises: storing data received in TS packets into an MPE-FEC frame buffer of a receiver according to locations indicated by an MPE-FEC frame buffer write pointer; and storing reliability information regarding said data separately therefrom, said reliability information including addresses of one or more locations in said MPE-FEC frame buffer to be marked for erasure. One such device is a receiver comprising an MPE-FEC frame buffer and an FEC decoder. The FEC decoder is configured to store data received in TS packets into the MPE-FEC buffer according to locations indicated by an MPE-FEC frame buffer write pointer. The FEC decoder is further configured to store reliability information regarding the data separately therefrom, the reliability information including addresses of one or more locations in the MPE-FEC frame buffer to be marked for erasure.

Error resilience methods for multi-protocol encapsulation forward error correction implementations

A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Video and graphics system with an MPEG video decoder for concurrent multi-row decoding

A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.

Video, audio and graphics decode, composite and display system

This invention describes a compilation method of extracting and implementing an accelerator control program from an application source code in a processor based system. The application source code comprises arrays and loops. The input application source code is sequential, with loop, branch and call control structures, while the generated output of this invention has parallel execution semantics. The compilation method comprises the step of performing loop nest analysis, transformations and backend processes. The step of loop nest analysis consists of dependence analysis and pointer analysis. Dependence analysis determines the conflicts between the various references to arrays in the loop, and pointer analysis determines if two pointer references in a loop are in conflict. Transformations convert the loops from their original sequential execution semantics to parallel execution semantics. The back-end process determines the parameters and memory map of the accelerator and the hardware dependent software.

Compiler method for extracting and accelerator template program

Transport stream (TS) packets containing sections of IP datagrams for an application level process are received and correct ones of said sections are stored into an MPE-FEC frame buffer of a receiver. Stored ones of said sections are reorganized within the frame buffer so as to leave appropriate positions, marked for erasure, within the frame buffer available for corrected data. Data bytes stored at the appropriate positions may be corrected using Reed-Solomon parity data stored in the frame buffer and then subsequently written back thereto.

Error concealment for motion picture expert group (MPEG) decoding with personal video recording functionality. The present invention is operable to perform error concealment of MPEG data within various components within playback, recording, reading and writing data systems. The present invention is operable within existing systems whose components may not be capable of accommodating errors within MPEG data. Whereas prior art systems typically cannot deal with any corruption without either losing the data or suffering some operational failure, the present invention is able to conceal these errors and to continue decoding and presentation of the MPEG data. In certain embodiments, this involves maximizing the available data that contain no errors to conceal those portions of the data that do include errors. The present invention is operable to accommodate various layers while performing error concealment, including the MPEG transport stream layer, the video layer, and the audio layer.

Systems and methods are provided for processing Multi-Protocol Encapsulation (MPE) under the DVB-H standard. The system includes: (a) a receive buffer having entries organized as columns and rows, the addresses for the entries in the receive buffer being arranged sequentially in column-major order; (b) a first process writing MPE data into the receive buffer, in the manner such that, for each frame, the application data portion and the error correction code portion are written sequentially in column major order, (c) a second process decoding the error correction code portion of each frame and which corrects the application data portion in accordance with the decoding; and (d) a third process reading out the application data portion from the receiver buffer column by column, the third process re-reading any column of the application portion that is corrected by the second process, when that column has previously been read by the third process.

Method and apparatus for memory optimization in MPE-FEC system

A method of reducing data transfer overheads in a 32-bit bus interface unit direct memory access architecture. The method comprises the steps of identifying the optimal number of data elements, that can be accessed as a single full-word transfer, setting data packing criteria and analysing the data pattern and determining the impact of offset direction on data packing. If the packing criteria are met, the data is compacted and fetched in four bytes or two half-words in one transaction by performing a full-word transfer instead of a partial transfer. If the packing criteria are not met, a single byte or a single half word is fetched. This invention provides a system for reducing data transfer overheads. The system comprises of an external address generation unit for generating external memory addresses and corresponding byte enables and a read local address generation unit for generating internal memory addresses and corresponding byte enables.

Data packing in a 32-bit DMA architecture

Presented herein is a system for storing macroblocks for such that all vertically, horizontally, and diagonally adjacent macroblock are stored in different banks. When fetching a block from a reference frame that overlaps four macroblocks, each of the overlapped macroblocks can be fetched substantially concurrently.

System, method, and apparatus for efficiently storing macroblocks

Presented herein is a scheme for reducing the likelihood of erroneous DQS signals. Logic is incorporated proximate to a memory controller and receives a signal indicating a read request and a DQS signal from a memory module. The logic transmits a signal indicating the presence of data, based on the timing relationship between the DQS signals and signal indicating read requests.

Dual numerically controlled delay logic for DQS gating

Growing community of inventors

Bengaluru, India

Ramanujan K Valmiki