Intel Corporation

Koninklijke Philips Corporation N.v.

Entropic Communications, Inc.

Nytell Software LLC

Koninklijke Philips Electronics N.v.

Intel Benelux B.v.

Ramanathan Sethuraman

Carlos Antonio Alba Pinto

Francesc Guim Bernat

Karthik Kumar

Harm Johannes Antonius Maria Peters

Balakrishnan Srinivasan

Brinda Ganesh

Aleksandar Beric

Rafael Peset Llopis

Ned M Smith

Mark A Schmisseur

Timothy Verrall

Suraj Prabhakaran

Ajaya V Durg

Jean-Pierre Giacalone

Arojit Roychowdhury

Hong Jiang

Thomas Willhalm

Andrew J Herdrich

Changliang Wang

Evan Custodio

Patrick G Kutch

Rajeev D Muralidhar

Nilesh K Jain

Sumit Mohan

Trevor Cooper

Ravi Iyer

Patrick Peter Elizabeth Meuwissen

Alexander Vul

Ignacio Astilleros Diez

Rakesh Avichal Ughreja

Srinivasan Balakrishnan

Zdravko Pantic

Anton Veselov

Marat Gilmutdinov

Vladimir Kovacevic

Gerard Veldman

Kevin Bohan

Marat Ravilevich Gilmutdinov

Anton Igorevich Veselov

Data management for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow a device, such as an endpoint or client device, or another edge resource, to specify criteria for managing data originating from the device and stored in an edge resource, and extends the storage and memory controllers to manage data in accordance with the criteria, including removing stored data that no longer satisfies the criteria. The criteria includes a temporal hint to specify a time after which the data can be removed, a physical hint to specify a list of edge resources outside of which the data can be removed, an event-based hint to specify an event after which the data can be removed, and a quality of service condition to modify the time specified in the temporal hint based on a condition, such as memory and storage capacity of the edge resource in which the data is managed.

Data management for edge architectures

Technologies for providing dynamic persistence of data in edge computing include a device including circuitry configured to determine multiple different logical domains of data storage resources for use in storing data from a client compute device at an edge of a network. Each logical domain has a different set of characteristics. The circuitry is also to configured to receive, from the client compute device, a request to persist data. The request includes a target persistence objective indicative of an objective to be satisfied in the storage of the data. Additionally, the circuitry is configured to select, as a function of the characteristics of the logical domains and the target persistence objective, a logical domain into which to persist the data and provide the data to the selected logical domain.

Technologies for providing dynamic persistence of data in edge computing

In one embodiment, an apparatus includes: a storage having a plurality of entries each to store address information of an instruction and a count value of a number of executions of the instruction during execution of code including the instruction; and at least one comparator circuit to compare a count value from one of the plurality of entries to a threshold value, where the instruction is a tagged instruction of the code, the tagged instruction tagged by a static compiler prior to execution of the code. Other embodiments are described and claimed.

System, apparatus and method for dynamic profiling in a processor

Technologies for managing telemetry and sensor data on an edge networking platform are disclosed. According to one embodiment disclosed herein, a device monitors telemetry data associated with multiple services provided in the edge networking platform. The device identifies, for each of the services and as a function of the associated telemetry data, one or more service telemetry patterns. The device generates a profile including the identified service telemetry patterns.

Technologies for managing sensor and telemetry data on an edge networking platform

Techniques related to frame re-ordering for video coding are described herein.

Method and system of frame re-ordering for video coding

Methods and apparatus to permit a system low power consumption state when CPU (Central Processing Unit) or generically any compute element is active are described. In an embodiment, a fabric and a memory controller are caused to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle. The entry into the low power consumption state occurs while a compute element, coupled to the fabric and the memory controller, is in an active state. Other embodiments are also disclosed and claimed.

Enabling system low power state when compute elements are active

The present disclosure describes techniques related to media caching. A media hub device may include a media hub device configured to execute an operation on a current frame of media having a frame period. The media hub device may include a cache configured to provide, to a media accelerator of the media hub device, data associated with the frame period of the current frame.

Media hub device and cache

A data processing system is provided for processing video data on a window basis. At least one memory unit (L) is provided for fetching and storing video data from an image memory (IM) according to a first window (R) in a first scanning order. At least one second memory unit (L) is provided for fetching and storing video data from the first memory unit (L) according to a second window in a second scanning order (SO). Furthermore, at least one processing unit (PU) is provided for performing video processing on the video data of the second window as stored in the at least one second memory unit (L) based on the second scanning order (SO). The second scanning order (SO) is a meandering scanning order being orthogonal to the first scanning order (SO).

Data processing system

Methods, apparatus, systems and articles of manufacture to perform block-based static region detection for video processing are disclosed. Disclosed example video processing methods include segmenting pixels in a first frame of a video sequence into a first plurality of pixel blocks. Such example methods can also include processing the first plurality of pixel blocks and a second plurality of pixel blocks corresponding to a prior second frame of the video sequence to create, based on a first criterion, a map identifying one or more static pixel blocks in the first plurality of pixel blocks. Such example methods can further include identifying, based on the map, a static region in the first frame of the video sequence.

Block-based static region detection for video processing

A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.

Data processing apparatus address range dependent parallelization of instructions

A programmable data processing circuit has a memory for storing pixel values, or more generally data values as a function of position in a signal. The programmable data processing circuit supports instructions that include an indication of a selected parameter value set that indicates how a plurality of data values must be arranged for parallel output from a memory. Instructions that indicate different parameter value sets can be executed intermixed with one another. The programmable data processing circuit responds to instructions of this type by retrieving the selected parameter value sets from a parameter storage circuit (), and controlling a switching circuit () between a memory port () of a memory circuit () and a data port () at least partly dependent on the selected parameter value set.

Programmable data processing circuit

A data buffering device which contains an input unit adapted to sequentially receive a two-dimensional array of data structures organized by an index pair with a first index stepwise traversing first-index values in a meandering manner defined by a first and a second meandering direction. The invention further includes a data buffering method, and a data processing method and device; each of which incorporates the above described features of the data buffering device.

Processing a data array with a meandering scanning order using a circular buffer memory

The data processing device has a plurality of functional units and issues instructions in successive instruction cycles. Instructions of a first type are each intended for one functional unit at a time. An instruction of a second type causes a combination of functional units to respond in the same instruction execution cycle, a result from one functional unit being used by another as part of the execution of the same instruction. Preferably, the device supports alternative operation at a number of different instruction cycle rates, dependent on whether an executed program segment contains instructions of the second type. The fastest instruction cycle rate does not allow execution of the instruction of the second type, because operation by different functional units does not fit within the instruction execution cycle. When possible, the device saves power by switching to a slower clock rate, in which case instructions of the second type are executed to save additional power, by reducing the number of instructions that have to be issued.

Data processing device with instruction controlled clock speed

Growing community of inventors

Bengaluru, India

Ramanathan Sethuraman