Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Westem Digital Technologies, Inc.

Ramanathan Muthiah

Yehuda Hahn

Ramkumar Ramamurthy

Daniel Joseph Linnen

Akhilesh Yadav

Kirubakaran Periyannan

Niraj Srimal

Adarsh Sreedhar

Balaji Thraksha Venkataramanan

Eldhose Peter

Rakesh Balakrishnan

Dinesh Kumar Agarwal

Narendhiran Chinnaanangur Ravimohan

Vimal Kumar Jain

Hitesh Golechchha

Laxmi Bhoopali

Dattatreya B Nayak

Pavan Gururaj

Dinesh Babu

Sridhar Sabesan

Ronak Jain

Pradeep Sreedhar

Bala Siva Kumar Narala

Bhavya Krishna

Nikita Thacker

Kshitij Gupta

Noor Mohamed Aa

Gautam Ashok Dusija

Rotem Sela

Niles Yang

Stella Achtenberg

Mark Shlick

Nitin Jain

Muralitharan Jayaraman

Matthew Harris Klapman

Raghavendra Gopalakrishnan

Abhijit K Rao

Ankur Agrawal

Vered Kelner

Kalpit Bordia

Jonathan Journo

Lakshmi Sowjanya Sunkavelli

Arun Kumar Shukla

Yogesh Tayal

Venkatesh Naidu Pamoti

Rohit Prasad

Manoj M Shenoy

Savita H Neelannavar

Pradeep Seetaram Hegde

Anil Kumar Kolar Narayanappa

Bhanushankar Doni Gurudath

Taninder Singh Sijher

Nagaraj Dandigenahalli Rudrappa

Prashanth Reddy Enukonda

Narendra Bayanaboina

Gnanasekar Rajakumar

Grant Chapman Mackey

Subash Rajaram

Abhishek Shetty

Nikhil Ranjan

Naveen Subbegoundanputhur Krishnaraj

Bhuvanesh Subramanian

Ravi Gaja

Sundararajan Rajagopal

Gopi Kuppan Thirumalai

Narendra Darapureddy

Sachin Krishna Kudva

Jacob Albons

Ashim Ranjan Saikia

Rajesh Neermarga

Instead of all the NAND memory having asynchronous independent plane read (AIPR) enabled, a system utilizes a master-SSD to route data to multiple client SSDs via a controller memory buffer (CMB) according to the underlying NAND hardware (HW) of each of the client SSDs. The master-SSD will also analyze the application data retrieval of the logical data that is to be routed. The system comprises SSDs with AIPR NAND circuitry and SSDs with non-AIPR NAND circuitry. The system further comprises the master-SSD that will route data to any of the SSDs in the system based on the data retrieval type (sequential or random). Each of the SSDs can be of a different type beyond the NAND chip, such as HW IPs or specific firmware (FW) that is tuned towards specific data routing and retrieval requirements.

Data routing in networked SSDs

A data storage device and method for host-assisted deferred defragmentation and system handling are provided. In one embodiment, the data storage device comprises a memory and a controller. The controller is configured to receive, from a host, a plurality of write commands and a grouping identifier associated with the plurality of write commands, wherein the plurality of write commands comprise a plurality of non-sequential logical block addresses and a plurality of sequential segments of a file; and in response to the grouping identifier being associated with the plurality of write commands, execute the plurality of write commands by storing the plurality of sequential segments of the file sequentially in the memory even though the logical block addresses associated with the segments of the file are non-sequential. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Data storage device and method for host-assisted deferred defragmentation and system handling

Aspects of a storage device are provided for efficient handling of logical metablock formation based on a heat distribution within the storage device. The storage device includes a plurality of memory dies each including a physical block, and a controller which forms a logical metablock from the physical blocks based on a location of each of the memory dies with respect to the controller. The controller stores a mapping of heat credit points to each of the physical blocks, where each of the heat credit points are associated with a respective heat level. The controller forms logical metablocks from the physical blocks based on the mapping. For instance, the controller forms different logical metablocks from physical blocks based on respective heat levels associated with memory dies including those blocks. As a result, efficient logical block formation may be achieved without significant complexity in firmware implementation.

Die location based logical block formation and handling

Systems, video cameras, and methods for predictive adjustment of multi-camera surveillance video data capture are described. A plurality of networked video camera is deployed with known spatial relationships and non-overlapping fields of view among cameras. When a video event is detected from video data for one of the video cameras, a video capture update message is selectively sent to other video cameras to modify their video capture operations. For example, an object detected by one camera may trigger adjustment of video capture operating parameters for cameras in a direction of travel of the object before it has entered the field of view of those other cameras.

Predictive adjustment of multi-camera surveillance video data capture

A key-value storage device may perform error-handling on key-value data stored in a memory device. The key-value storage device may be communicatively coupled to a host device that may transmit read commands to retrieve the key-value data stored on the memory device. In response to a read command, the storage device may retrieve the key-value data from the memory device. If during retrieval the storage device identifies that a portion of the key-value data is irretrievable, the storage device may perform an error-handling operation on the key-value data. Depending on a key-value data type, the storage device may perform an error concealment operation and return complete key-value data or a partial error-handling operation and return partial key-value data to the host.

Error handling in key-value solid state drives

A multi-tier memory comprises a block of memory with a plurality of sub-blocks (e.g., three sub-blocks). A garbage collection operation that chooses a source block based on a valid fragment count may not be suitable in multi-tier memories where sub-blocks have a dependency on one another (e.g., for an erase or program operation). The embodiments presented herein provide various garbage collection techniques that can be used in this situation. The techniques described herein can take in to account the valid fragment count of various sub-block groupings when deciding where to perform a garbage collection operation.

Data storage device and method for garbage collection in a multi-tier memory

A data storage device having a flash translation layer configured to handle file-system defragmentation in a manner that substantially avoids physical data movement in a flash memory. In an example embodiment, a memory controller operates to update a logical-to-physical table thereof to change association of physical addresses of sections of user data from being associated with source logical addresses to being associated with destination logical addresses of the host defragmentation requests without moving the user data in the flash memory. Such updates can reduce the number of instances in which the host addresses a non-contiguous logical-address range, which results in a beneficial reduction of the number of input/output commands sent to the data storage device and of the associated processing overhead.

Logical-to-physical mapping for defragmentation of host file system in a data storage device

A storage system and method for storage management in multi-channel, variable-bit-rate systems are provided. In one embodiment, a host is provided comprising a first interface configured for communication with a storage system; a second interface configured for communication with a video capture device; and a processor. The processor is configured to receive an internal latency estimate from the storage system; use the internal latency estimate from the storage system to determine whether a rate of data generation by the video capture device exceeds a storage rate of the storage system; and in response to determining that the rate of data generation by the video capture device exceeds the storage rate of the storage system, instruct the video capture device to lower its rate of data generation. Other embodiments are provided.

Storage system and method for storage management in multi-channel, variable-bit-rate systems

A data storage device comprising a data port, configured to transceive data via a wired communication channel, a control port, configured to transceive data via a peer-to-peer wireless communication channel, a non-volatile storage medium, and a controller. In response to receiving, from a user device, via the control port, a command to enable control channel access, the controller performs an unlocking process, and, in response to completing the unlocking process, transitions from a locked state to a control channel access state. In response to being in the control channel access state, and in response to receiving, from the user device, via the control port, a write command, the controller stores write data in the storage medium, and, in response to receiving, from a host computer, via the data port, a command to access the storage medium, the controller transmits, to the host computer, a locked state indication.

Method and device for secure data transfer and storage

When copy commands are queued in a submission queue, there can potentially be many queued input-output (I/O) commands directed to the same logical range as the queued commands. This can result in data being invalidated immediately after it is written in memory, leading to write amplification and inefficient backend processing. To address this problem, the embodiments presented herein can be used to lock the range of logical block addresses of the queued commands, so that I/O commands are prevented from accessing the range of logical block addresses until the queued copy commands are completed.

Data storage device and method for logical range lock

Various embodiments of this disclosure are directed to a mixed digital and analog domain approach to computational storage or memory applications. The mixed approach enables certain compute operations to be advantageously performed in the analog domain, achieving power saving. In some embodiments, an analog compute core is implemented based on a first set of memory elements that are made available with a second set of memory elements for digital data storage. A controller coupled to both sets of memory elements is able to selectively direct computational tasks to either the analog compute core or a digital processor coupled with the controller, based on one or more parameters including power, precision, and workload. In certain embodiments involving neural network tasks, the controller is configured to route certain tasks to the analog compute core based on neural network based factors such as network layer positioning and input signal type.

Adaptive mixed digital and analog computational storage systems

A storage device may be coupled to a host device and the storage device may support a host performance booster (HPB) feature. A controller on the storage device may execute a background relocation operation. During the background relocation operation, the controller may identify a block to relocate data from. The controller may also determine that a relocation system threshold has not been reached. The controller may execute a source selection algorithm configured to minimize HPB entry inactivation resulting from data relocation. The source selection algorithm may include a criterion to enable the controller to select a source block for relocation.

Read access management of host performance booster (HPB) regions by a storage device

A data storage device is described that can be configured with various techniques to release a source block to a free block pool even if the source block contains an uncorrectable error in an address header in one of its clusters that would otherwise prevent the release of the source block. The various techniques can be used individually or in combination.

Data storage device and method for releasing a source block having an uncorrectable error

Some data storage devices have a plurality of memory dies that can be read in parallel for certain types of read requests. Read requests pertaining to a garbage collection operation are often generated sequentially and, thus, are not eligible for parallel execution in the memory dies. In an example data storage device presented herein, such read requests are consolidated and sent to the memory for execution in parallel across the memory dies.

Data storage device and method for improving asynchronous independent plane read (AIPR) utilization

A data storage device can store data and parity information for the data in its memory. In some storage methodologies, data and parity information are striped across a plurality of memory dies (e.g., in a redundant array of independent drives (RAID) configuration). That way, if one of the memory dies fails, the data or the parity information can be reconstructed from the other memory dies. These embodiments recognize that because parity information is used relatively infrequently, the parity information can be stored in locations in the memory that have a relatively-worse performance than other areas of the memory. This can increase performance of the memory in situations where the parity information does not need to be read.

Data storage device and method for performance-dependent storage of parity information

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Bengaluru, India

Ramanathan Muthiah