Intel Corporation

Raman Nayyar

Douglas Raymond Moran

Leonard W Cross

Suvansh Krishan Kapur

Kenneth C Holland

Howard S David

Eric Dahlen

Ali S Oztaskin

Warren Morrow

Jayamohan Dharanipathi

A block of data may be transferred to memory through a plurality of write operations, where each write operation is preceded by a protocol request and a protocol response. A plurality of protocol requests issued in a first order may elicit a corresponding plurality of protocol responses in a second order, and the write operations may be performed in yet a third order. Chipsets implementing the data write methods are also described and claimed.

Method and apparatus for memory write performance optimization in architectures with out-of-order read/request-for-ownership response

Methods of obtaining, enqueueing and executing several memory transactions are described, where the memory transactions may be generated in a first order but executed in a second order. Despite the relaxed ordering, essential programming paradigms such as producer-consumer relationships are not affected. Chipsets and systems using the methods are also described and claimed.

Method and apparatus for exploiting parallelism across multiple traffic streams through a single channel

An apparatus and method for controlling data traffic flow and data ordering of packet data between one or more peripheral devices and a processor/memory combination by using a packet processing engine, located within an input-output hub (IOH). The IOH may include a packet processing engine, and a switch to route packet data between the one or more peripheral devices and the packet processing engine. The packet processing engine of the IOH may control data traffic flow and data ordering of the packet data to and from the one or more peripheral devices through the switch and also maintains flow and ordering to the processor/memory subsystem. The packet processing engine may be operable to perform packet processing operations, such as virtualization of a peripheral device or Transmission Control Protocol/Internet Protocol (TCP/IP) offload.

Transaction flow and ordering for a packet processing engine, located within an input-output hub

Some embodiments of the invention accurately account for power dissipation in memory systems that include individual memory modules by keeping track of the number of read requests, the number of write requests, and the number of activate requests that are applied to the individual memory modules during selected time periods. If the sum of these totals exceeds a threshold level, the embodiments throttle the memory system, either by throttling the entire memory system based in response to the most active memory module, or by throttling individual memory modules as needed. Other embodiments of the invention may assign the same or different weights to activate requests, read requests, and write requests. Other embodiments are described and claimed.

System and method for thermal throttling of memory modules

A method and apparatus are provided for performing address translation in an input/output (I/O) expansion bridge. The I/O expansion bridge includes a first interface unit, a second interface unit, and an address translation unit. The first interface unit is configured to be coupled to a system memory and I/O controller through one or more I/O ports. The first interface unit enables data transfers over the one or more I/O ports to or from the main memory of a computer system. The second interface unit provides bus control signals and addresses to enable data transfers over a bus to or from a peripheral device. The address translation unit is coupled to the first interface unit and the second interface unit. The address translation unit translates addresses associated with transactions received on the second interface by accessing a local memory containing physical addresses of pages in the main memory of the computer system.

Graphics address relocation table (GART) stored entirely in a local memory of an input/output expansion bridge for input/output (I/O) address translation

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Hillsboro, OR, United States of America

Raman Nayyar