Texas Instruments Corporation

Ramamurthy Vishweshwara

Venkatraman Ramakrishnan

Abhijit Anant Patki

Anand Kannan

Anand Subramanian

Arvind Nembili Veeravalli

Pedro Ramon Gelabert

Uttam Kumar Agarwal

Pramod Kumar Baskar

Mahita Nagabhiru

H Udayakumar

Diljith Mathal Thodi

An analog-to-digital converter (ADC) includes a capacitive digital-to-analog converter (CDAC), a comparator, and a successive approximation register (SAR) control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an output of the comparator and to an input of the CDAC. The SAR control circuit includes a flip-flop. The flip-flop includes a clock input terminal, a data input terminal, and an output. The clock input terminal is coupled to the output of the comparator. The data input terminal coupled to a constant voltage source. The flip-flop can include an enable input terminal coupled to a SAR state circuit. The output is coupled to the CDAC.

Analog-to-digital converter decision control

A circuit includes a programmable gain amplifier (PGA) having a PGA output. The circuit further includes a delta-sigma modulator having an input coupled to the PGA output. The circuit also includes a digital filter and a dynamic range enhancer (DRE) circuit. The digital filter is coupled to the delta-sigma modulator output. The DRE circuit is coupled to the delta-sigma modulator output and to the PGA. The DRE circuit is configured to monitor a signal level of the delta-sigma modulator output. Responsive to the signal level being less than a DRE threshold, the DRE circuit is configured to program the PGA for a gain level greater than unity gain and to cause the digital filter to implement an attenuation of a same magnitude as the gain level to be programmed into the PGA.

Analog-to-digital converter with dynamic range enhancer

Gating clocks has been a widely adopted technique for reducing dynamic power. The clock gating strategy employed has a huge bearing on the clock tree synthesis quality along with the impact to leakage and dynamic power. This invention is a technique for clock gate optimization to aid the clock tree synthesis. The technique enables cloning and redistribution of the fanout among the existing equivalent clock gates. The technique is placement aware and hence reduces overall clock wire length and area. The technique involves employing the k-means clustering algorithm to geographically partition the design's registers. This invention improves the clock tree synthesis quality on a complex design.

Placement aware clock gate cloning and fanout optimization

An aspect of the present invention selects a maximum voltage and a minimum voltage in respective sub-intervals of a timing window in which an output of a cell is expected to switch, and performing timing analysis based on the selected maximum voltage and the selected minimum voltage. By using appropriate smaller sub-intervals within the timing window, more optimal physical layout of the design may be obtained. In an embodiment, the sub-intervals equal a cell delay, i.e., a delay between an input change to an output change for a corresponding cell. According to another aspect of the present invention, the sub-interval for later cells in a timing path are modified based on a modified timing window of previous cells in the timing path, to reduce the computational requirement.

IC design flow incorporating optimal assumptions of power supply voltage drops at cells when performing timing analysis

Growing community of inventors

Bengaluru, India

Ramamurthy Vishweshwara