Kepler Computing Inc.

Bell Communications Research, Inc.

University System of Maryland

Other

University of California

International Business Machines Corporation

Motorola Corporation

Lucent Technologies Inc.

Telcordia Technologies, Inc.

Candescent Technologies Corporation

Candescent Intellectual Property Services, Inc.

Tachyon Semiconductor Corporation

Tachyon Semiconductors Corporation

Ramamoorthy Ramesh

Sasikanth Manipatruni

Rajeev Kumar Dokania

Amrita Mathuriya

Robert Menezes

Gaurav Thareja

Yuan-Sheng Fang

Rafael Rios

Ikenna Odinaka

Niloy Mukherjee

Jason Y Wu

Gabriel Antonio Paulius Velarde

Fnu Atiquzzaman

Noriyuki Sato

Sanjeev Aggarwal

Neal Reynolds

Tanay Gosavi

Somilkumar J Rathi

Pratyush Pandey

Mauricio Manfrini

Zeying Ren

Arun Inam

James Clarkson

Anil M Dhote

James David Clarkson

Charles T Rogers, Jr

Debraj Guhabiswas

Scott Robert Perusse

Maria Isabel Perez

Sungho Jin

Alejandro Gabriel Schrott

Christopher J Spindt

James C Dunphy

Jean-Marie Tarascon

Ravindranath Droopad

Michael James Nystrom

Zhiyi Jimmy Yu

Kurt W Eisenbeiser

Timothy David Sands

Shiyou Pei

Roger W Barton

Kollengode S Narayanan

Mark T McCormack

George B Hopple

Lawrence S Pan

James Anthony Misewich

Arunava Majumdar

Donald R Schropp, Jr

Choongho Yu

Darrell G Schlom

Jeffrey M Finder

John K O'Reilly

James P Harbison

Vasil M Chakarov

Yu Wang

Silas J Allen, Jr

Lane W Martin

Robert James Zeches

Guarav Thareja

Matthew L Scullin

Mark Huijben

Mark L Leadbeater

Saskikanth Manipatruni

A new class of multiplier cells (analog or digital) is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from first and second majority gates. The multiplier cell can also be implemented with a combination of two majority gates with majority and AND functions integrated in each of them. The two majority gates are coupled. Each of the first and second majority logic gates comprise a capacitor with non-linear polar material. The first and second majority gates receive the two inputs A and B that are to be multiplied. Other inputs received by the first and second majority gates are carry-in input, a sum-in input, and a bias voltage. The bias voltage is a negative voltage, which produces an integrated AND function in conjunction with a majority function. The second majority gate receives additional inputs, which are inverted output of the first majority gate.

Multiplier with non-linear polar material

Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.

Method of forming 3D stacked compute and memory with copper pillars

Non lead-based perovskite ferroelectric devices for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

High density ferroelectric random access memory (FeRAM) devices and methods of fabrication

Described is a low power, high-density non-volatile differential memory bit-cell. The transistors of the differential memory bit-cell can be planar or non-planer and can be fabricated in the frontend or backend of a die. A bit-cell of the non-volatile differential memory bit-cell comprises first transistor first non-volatile structure that are controlled to store data of a first value. Another bit-cell of the non-volatile differential memory bit-cell comprises second transistor and second non-volatile structure that are controlled to store data of a second value, wherein the first value is an inverse of the second value. The first and second volatile structures comprise ferroelectric material (e.g., perovskite, hexagonal ferroelectric, improper ferroelectric).

High-density low voltage ferroelectric differential memory bit-cell with shared plate- line

The memory bit-cell formed using the ferroelectric capacitor results in a taller and narrower bit-cell compared to traditional memory bit-cells. As such, more bit-cells can be packed in a die resulting in a higher density memory that can operate at lower voltages than traditional memories while providing the much sought after non-volatility behavior. The pillar capacitor includes a plug that assists in fabricating a narrow pillar.

Pillar capacitor and method of fabricating such

Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.

Integration of ferroelectric memory devices having stacked electrodes with transistors

A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

Apparatus with selectable majority gate and combinational logic gate outputs

Ferroelectric capacitor is formed by conformably depositing a non-conductive dielectric over the etched first and second electrodes, and forming a metal cap or helmet over a selective part of the non-conductive dielectric, wherein the metal cap conforms to portions of sidewalls of the non-conductive dielectric. The metal cap is formed by applying physical vapor deposition at a grazing angle to selectively deposit a metal mask over the selective part of the non-conductive dielectric. The metal cap can also be formed by applying ion implantation with tuned etch rate. The method further includes isotopically etching the metal cap and the non-conductive dielectric such that non-conductive dielectric remains on sidewalls of the first and second electrodes but not on the third and fourth electrodes.

Ferroelectric capacitor integrated with logic

A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. In some examples, the nodes of the non-linear input capacitors are conditioned once in a while to preserve function of the multi-input majority gates.

Method for conditioning majority or minority gate

A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

Rapid thermal annealing (RTA) methodologies for integration of perovskite-material based memory devices

An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.

Majority gate based low power ferroelectric based adder with reset mechanism

Method of fabricating a perovskite-material based planar capacitor using rapid thermal annealing (RTA) methodologies

Method of fabricating a perovskite-material based trench capacitor using rapid thermal annealing (RTA) methodologies

Rapid thermal annealing (RTA) methodologies for integration of perovskite-material based trench capacitors

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Moraga, CA, United States of America

Ramamoorthy Ramesh