The State University of New York

The Research Foundation of Suny at Buffalo

Ramalingam Sridhar

Yong-Chul Shin

Victor Demjanenko

Sargur N Srihari

Seokjin Kim

Zhang Xuguang

Cesar Bandera

Naidu C Bogineni

Shu Xia

Xuguang Zhang

Peter Scott

Paul W Palumbo

Dipankar Talukdar

A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

CMOS foveal image sensor chip

A family of CFET logic circuits useful for wave-pipeline systems is described, and a method to design same. The invention uses complementary transmission gates and pull-up or pull-down transistors to achieve a family of CFET logic circuits which include AND, NAND, OR, NOR, XOR, XNOR, select, select-invert, invert, and not-invert functions. Each circuit is tuned to provide substantially equal delays, high-quality ones and zeros, and substantially equal rise and fall times, for every combination of input-state transition and output-state transition.

Method and apparatus for designing circuits for wave pipelining

Logic circuits for wave pipelining

The invention relates to the design and operation of local clock control circuits which operate to supply a local clock signal to a controlled block of a digital circuit in response to an enable signal representative of an enable condition. The invention is embodied in several alternative local clock control circuits which comprise a signal joining means or a signal joining means in combination with an enable signal relay means. The signal joining characteristics of the Muller C-element are used advantageously in several embodiments. The invention serves to ease constraints on the arrival time of an enable signal at the local clock control circuit.

Method and apparatus for selective clocking using a Muller-C element

The problem of thresholding is considered from a clustering point of view and a novel weight-based clustering method (WCThresh) is implemented in a neural network image processor 50. The neural network image processor 50 uses weights 51-53, representing clusters of gray scale pixels of an image of document 43, to provide a threshold for the image of document 43. The processor 50 modifies weights 51-53 with the input pixels and comparator 60 using a nearest value criterion to provide the threshold.

Global threshold method and apparatus

A neural network provides both linearly separable and non-linearly separable logic operations, including the exclusive-or operation, on input signals in a single layer of circuits. The circuit weights the input signals with complex weights by multiplication and addition, and provides weighted signals to a neuron circuit (a neuron body or some a) which provides an output corresponding to the desired logical operation.

Single layer neural network circuit for performing linearly separable

Complementary field-effect transistor logic circuits for wave pipelining

In a mail sorting system 10, output pixel intensities of an optical scanner 18 have their contrast locally enhanced. A contrast enhancer 24 uses statistical methods (averaging, standard deviation) coupled with empirical stretch and offset data stored in a ROM 25, to enhance pixel contrast in a pipelined processing operation.

Local adaptive contrast enhancement

A neural network provides both linearly separable and non-linearly separable logic operations, including the exclusive-or operation, on input signals in a single layer of circuits. The circuit weights the input signals with complex weights by multiplication and addition, and provides weighted signals to a neuron circuit (a neuron body or soma) which provides an output corresponding to the desired logical operation.

An analog synapse circuit for an artificial neural network requiring less circuitry and interconnections than prior synapses, while affording better weight programming means uses two complementary floating-gate MOSFETs with tunneling injection in an inverter configuration, with each MOSFET storing a weight value. This weight value is set by storing a charge injected by Fowler-Nordheim tunneling, or other tunneling means, into the floating-gate, which shifts the threshold voltage of the device. A programming line applies a current pulse to the MOSFET floating gate to write or erase this stored charge, thereby adjusting the weight of the MOSFET. The two MOSFETs are connected with the gate electrodes connected together and the drain electrodes connected together to provide a common gate and common drain between the two MOSFETs. An input line is connected to the common gate, and an output line is connected to the common drain. The source electrodes of each MOSFET are connected to reference voltages. The synapse circuit may be used in either a feedforword or feedback network, and may be expanded from two to four quadrant operation. The synapse provides a single output current line which represents a function of the input voltage and the stored weights. A plurality of such synapses may be configured in a network, wherein the output lines of each synapse are connected at a current summing node at the input of a neuron. An active load in the input of the neuron allows for both excitatory and inhibitory output current from the synapse circuit.

Programmable analog synapse and neural networks incorporating same

A digital data memory unit and memory unit array, each unit of which can be searched in accordance with the contents thereof and updated, utilizes a digital storage element in the form of a register, latch, or memory cell, a comparator and control logic. Data is presented to the units in parallel on data lines and compare data is supplied in parallel to the units along other data lines. Parallel search of data in each unit, with multiple updates in units where the stored data matches the compare data, occurs rapidly and in one clock cycle (e.g., approximately 50 nanoseconds). The control logic responds to a match output from the comparator and an update enable pulse to enable a new data word on the data lines to be written into the digital storage element of the unit. The memory unit array is useful in image processing for storing pixel values and searching and updating these values in the process of image analysis to recognize certain images.

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East Amherst, NY, United States of America

Ramalingam Sridhar