Synopsys, Inc.

Ramalingam Kolisetti

Anubhav Sinha

Abhijeet Samudra

Salvatore Talluto

Amit Gopal M Purohit

Ajay Nagarandal

Jatin Verma

Sai Manish Rao Marru

Saransh Nagaich

Naresh Thakur

Sahil Soni

Milin Kaushik Raijada

Luis M Cruz

Yongkang Hu

Systems, integrated circuits and methods for synchronizing testing a Device under test (DUT) with an automated test equipment (ATE) is provided. In one example, a method includes transmitting a test packet from an ATE to a first Device Under Test DUT; receiving, at the ATE from the DUT, a result packet; and in response to receiving a Start of Packet (SOP) indicator from the DUT at the ATE, evaluating the first DUT by comparing the result packet to an expected packet associated with the test packet.

Device under test synchronization with automated test equipment check cycle

Test packets may be received at a design under test (DUT) from an automated test equipment (ATE) over a serializer/deserializer (SERDES) connection between the ATE and the DUT. The test packets may include test pattern data to test the DUT. The test pattern data may be applied to the DUT using a set of scan chains and test response data corresponding to the test pattern data may be obtained. The test response data may be received by a circuit in the DUT at irregular time intervals. Response packets may be sent to the ATE by the circuit in the DUT at regular time intervals, where the response packets may include a portion of the test response data (which may be encoded using an encoding technique), and where the response packets may be sent to ATE over the SERDES connection.

Deterministic data latency in serializer/deserializer-based design for test systems

Techniques for testing an integrated circuit (IC) are disclosed. A controller in the IC retrieves first testing data from a first memory in the IC. The controller transmits the first testing data to a first built-in self-test (BIST) core. The controller receives a response from the first BIST core, relating to a test at the first BIST core using the first testing data. The controller determines a status of the test relating to the IC based on the response.

Packetized power-on-self-test controller for built-in self-test

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Karempudi, India

Ramalingam Kolisetti