Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Conopco, Inc.

Infinera Corporation

Ramakrishnan Subramanian

Nitin Kumar Gupta

Shiv Harit Mathur

Vinayak Ashok Ghatawade

Sitaram Banda

Yan Li

Rajan Rao

Venkatesh Ramachandra

Dmitry Vaysman

Nikhil Kumar Satyarthi

Sanjeev Ramachandran

Baranidhar Ramanathan

Elkana Richter

Jayaprakash Naradasi

Anand Venkitachalam

Vijay Chinchole

Jayanth Mysore Thimmaiah

Parveen Kumar Gupta

Rampraveen Somasundaram

Sumana Roychowdhury

Ashish Savadia

Prashant Singhal

Nivedita Jagdish Patil

Siva Raghu Ram Voleti

Siddesh Darne

Sowmya Mahadevaiah

Sujoy Bej

Saheli Chakraborty

An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or both of the transistors and one of the supply levels, with a capacitor connected between the low supply level and a node between the resistor and the transistor. The resistor helps to isolate the transistor from the supply level while the capacitor can act as current reservoir to boost the current to the transistor during data transition, reducing the noise seen by the voltage supply.

High speed toggle mode transmitter with capacitive boosting

The invention provides an itaconate surfactant having the following formula (I) in which Ris selected from aliphatic hydrocarbyl groups having 4 to 22 carbon atoms; Ris selected from hydrogen and aliphatic hydrocarbyl groups having 1 to 4 carbon atoms; and n is an integer ranging from 8 to 20. The surfactants of the invention are benign to the skin and to the environment yet can offer a performance that is comparable to that of 'traditional' anionic and anionic/nonionic surfactant systems, especially on difficult-to-remove stains.

Itaconate surfactants

Various apparatuses, systems, methods, and media are disclosed to provide over-voltage protection to a data interface of a multi-protocol memory card that includes a first communication interface and a second communication interface that enable communication using different protocols. An interface voltage protection circuit includes a control circuit configured to receive a first supply voltage for operating the first communication interface. The interface voltage protection circuit further includes a pull-down circuit operatively connected with the control circuit, configured to pull down a voltage at a supply voltage rail of the second communication interface such that a voltage at a plurality of connector terminals of the second communication interface is lower than the first supply voltage.

High voltage protection for high-speed data interface

The disclosure relates in some aspects to electrostatic discharge (ESD) protection for an electronic circuit. In some aspects, the ESD protection includes a buffer circuit that increases the slew rate of a signal that controls a discharge circuit. In some aspects, the ESD protection includes a voltage-dependent resistance circuit that adjusts a time constant of a resistive-capacitive filter based on a voltage on a supply node.

Electrostatic discharge protection circuit

A data storage system includes a storage medium including plurality of memory cells, a storage controller in communication with the storage medium, an electrical interface circuitry configured to pass data via a channel disposed between the storage medium and the storage controller; and voltage training circuitry configured to train a high-level output voltage (VOH) for each of a plurality of data lines of the channel. Training the VOH includes, for each of the plurality of data lines of the channel, calibrating a pull-up driver of the storage controller against an on-die termination circuit of the storage medium, calibrating a pull-down driver of the storage controller against the pull-up driver of the storage controller, and calibrating an on-die termination circuit of the storage controller against a pull-up driver of the storage medium.

High-level output voltage training for non-volatile memory

A data storage system includes a memory including a plurality of memory cells; and an interface coupled to the memory and a host. The interface includes a multi-level transmission encoder configured to receive an input data signal from the host and encode the input data signal as a multi-level data signal. The interface further includes a multi-stage driver network including a plurality of driver stages, wherein each driver stage of the plurality of driver stages is configured to apply an impedance or forego applying an impedance to the multi-level data signal based on a previous state and a current state of the multi-level data signal.

Multi-level signaling scheme for memory interface

A methodology and structure for a encoding a data stat signal in the data lock signal, e.g., the data strobe signal such as DBQ. The data strobe signal can maintain the clock continuity, e.g., the rise and fall edges are at the timing signal, and the data inversion can be based on the amplitude of the data strobe signal. This allows the data set on the data lines, e.g., D-D, to either be non-inverted or inverted, to save power consumed in the memory device.

Transmitting DBI over strobe in nonvolatile memory

An illustrative embodiment disclosed is a circuit including an edge-triggered flip-flop having a first input port, a first clock port, and a first output port. The edge-triggered flip-flop receives, at the first clock port, a strobe having a first edge and a second edge. The edge-triggered flip-flop receives, at the first input port, a control byte time-aligned with the first edge and a data byte time-aligned with the second edge. The edge-triggered flip-flop passes, to the first output port, the control byte based on the first edge and the data byte based on the second edge. The circuit includes an inputs/outputs (I/O) decoder coupled to the first output port. The I/O decoder sends the control byte to microcontroller and sends the data byte to memory cells.

System and method for a reconfigurable controller bridge chip

Embodiments include methods and apparatuses for providing at least one signaling indication of a super-channel by a power controller in a Wavelength Division Multiplexing (WDM) system. The power controller may receive a service provisioning and a lock state from a network management entity. The power controller may receive, from an optical fabric unit, a fabric state that indicates whether a pass-band of the super-channel is provisioned. The power controller may receive the power level of the super-channel from a power monitoring unit. Based on the power level and attenuation level of the super-channel, the power controller may determine a ramp state that indicates whether the power level reached to a predetermined power. The power controller may determine an alarm state based on the power level. The power controller may determine the signaling indication based on the service provisioning, lock, fabric, ramp, and alarm states.

Method and system for signaling defects in a network element with optical fabric

Apparatuses, systems, methods, and computer program products are disclosed for on-die impedance calibration. A calibration circuit determines a digital compensation value for an input/output driver. A calibration adjustment circuit provides a digital compensation value to a calibration circuit to produce an analog output corresponding to the digital compensation value. A feedback circuit provides an analog output as feedback to a calibration circuit to produce an analog compensation value.

On-die impedance calibration

Methods and circuits for delay compensation are provided. A data clock may be generated from a peripheral clock. Sample data may be provided in a data signal on a bus in response to an edge of the data clock, where the edge of the data clock is triggered by an initial edge of the peripheral clock. A delay of the data clock relative to the peripheral clock may be selected based on a time difference between the initial edge of the peripheral clock and a time at which the sample data is detected on the bus. A delayed data clock having the selected delay relative to the peripheral clock may be generated. Requested data may be provided on the bus in response to an edge of the delayed data clock.

Growing community of inventors

Bengaluru, India

Ramakrishnan Subramanian