Intel Corporation

Ramakrishnan Sivakumar

Guy M Therien

Russell Jerome Fenger

Premanand Sakarda

Rajshree Chabukswar

Deepak Samuel Kirubakaran

Monica Gupta

Jianwei Dai

Vijay Dhanraj

Renji Thomas

Chad Gutierrez

A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.

Hardware and software coordinated cost-aware low power state selection

Systems, apparatuses and methods may provide for technology that identifies a thread and selects a core from a plurality of processor cores in response to the selected core being available while satisfying a least used condition with respect to the plurality of processor cores. The technology may also schedule the thread to be executed on the selected core.

Technology to augment thread scheduling with temporal characteristics

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Hillsboro, OR, United States of America

Ramakrishnan Sivakumar