Microsoft Technology Licensing, LLC

Ramakoti R Bhimanadhuni

Mallik Bulusu

Bryan David Kelly

Emily Nicole Wilson

Muhammad Ashfaq Ahmed

Brett Kenneth Dodds

Daniel Sebastian Berger

Ravi Mysore Shantamurthy

John A Strange

Pingfan Song

Peter Hanpeng Jiang

Pallavi Baral

Bhuvan Malladihalli Shashidhara

Sebastien Nathan R Levy

Josh Charles Moore

Ahu Oral

Arhatha Bramhanand

Juan Arturo Herrera Ortiz

Christina Margaret Tobias

Brijesh Ramachandran

Charlotte Gauchet

Jasmine Grace Schlichting

Michael Wayne Stephenson

Farah Farzana

The disclosure herein describes training and using an uncorrectable error (UE) state prediction model based on telemetry error data. Sets of UE state labels and non-UE state labels are generated from a first set of collected telemetry data, wherein the UE state labels each reference a UE and telemetry data of an interval prior to the referenced UE. Statistical features are extracted from telemetry data of the sets of UE state labels and non-UE state labels, and the extracted statistical features are used to train a UE state prediction model. A second set of collected telemetry data is obtained, and a UE event is predicted based on the second set of collected telemetry data using the trained UE state prediction model. A preventative operation is performed on a memory page of the system based on the predicted UE event, whereby the predicted UE event is prevented from occurring.

Training and using a memory failure prediction model

A computing device is provided, including memory storing an instruction storage location. The computing device may further include a processor system including a plurality of processor threads. The processor system may suspend execution of one or more respective processor threads of the plurality of processor threads. The processor system may store one or more respective processor thread contexts of the one or more processor threads in the memory. The processor system may enter a system management mode (SMM). The processor system may determine that the instruction storage location includes a code update instruction. The processor system may perform a code update based on the code update instruction. The processor system may exit the SMM. The processor system may retrieve the one or more processor thread contexts from the memory and resume execution of the one or more processor threads without rebooting the computing device.

Code update in system management mode

Example techniques for updating a firmware, such as BIOS, are disclosed. Upon receiving an update, it is determined whether a secondary non-volatile memory is defined for the firmware. If the secondary non-volatile memory is defined, the update may be written in the secondary non-volatile memory. Further, to apply the update, a warm reboot of the firmware may be performed. The warm reboot causes an OS of the computing system to restart, while preserving data associated with applications running on the computing system.

Firmware update

Systems and methods are disclosed for an initialization process that selectively reloads part or all of the UEFI when called by the operating system. The reload skips platform initialization and enables the selective loading of UEFI modules with tailored dependencies. A special protected region of memory is reserved and is not available for use by the host operating system. Once initialized, the UEFI will use the reserved memory region to execute code that initiates or loads UEFI modules. The host operating system will await the UEFI reload and then re-initialize the functions, structures and variables it receives from the UEFI.

Optimized UEFI reboot process

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Redmond, WA, United States of America

Ramakoti R Bhimanadhuni