Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Ramachandramurthy Pradeep Yelehanka

Rakesh Kumar

Zouhair Sbiaa

Humberto Campanella-Pineda

Weining Li

Jia Jie Xia

Shailendra Mishra

Nagarajan Ranganathan

Siddharth Chakravarty

Aveek Nath Chatterjee

Sripad Sheshagiri Nagarad

Tin Tin Wee

Lin Yung Tao

Minu Prabhachandran Nair

Microelectromechanical System (MEMS) devices and related fabrication methods. A piezoelectric stack is formed on a substrate and is separated from the substrate by a dielectric layer. The piezoelectric stack is formed that includes first and second piezoelectric layers with a first electrode below the first piezoelectric layer, as well as a contact pad and a second electrode between the first and second piezoelectric layers. A first contact is formed that extends through the piezoelectric layers and contact pad to the first electrode. A second contact is formed that extends through the second piezoelectric layer to the second electrode. The contact pad prevents an interface to form between the first and second piezoelectric layers in the contact opening, thus preventing corrosion of the piezoelectric layers during contact formation process.

Fabrication methods for a piezoelectric micro-electromechanical system (MEMS)

Integrated circuits having shielded micro-electromechanical system (MEMS) devices and method for fabricating shielded MEMS devices are provided. In an example, an integrated circuit having a shielded MEMS device includes a substrate, a ground plane including conductive material over the substrate, and a dielectric layer over the ground plane. The integrated circuit further includes a MEMS device over the ground plane. Also, the integrated circuit includes a conductive pillar through the dielectric layer and in contact with the ground plane. The integrated circuit includes a metallic thin film over the MEMS device and in contact with the conductive pillar, wherein the metallic thin film, the conductive pillar and the ground plane form an electromagnetic shielding structure surrounding the MEMS device. Further, the integrated circuit includes an acoustic shielding structure over the substrate and adjacent the electromagnetic shielding structure.

Integrated circuits having shielded MEMS devices and methods for fabricating shielded MEMS devices

Three-axis monolithic microelectromechanical system (MEMS) accelerometers and methods for fabricating integrated capacitive and piezo accelerometers are provided. In an embodiment, a three-axis MEMS accelerometer includes a first sensing structure for sensing acceleration in a first direction. Further, the three-axis MEMS accelerometer includes a second sensing structure for sensing acceleration in a second direction perpendicular to the first direction. Also, the three-axis MEMS accelerometer includes a third sensing structure for sensing acceleration in a third direction perpendicular to the first direction and perpendicular to the second direction. At least one sensing structure is a capacitive structure and at least one sensing structure is a piezo structure.

Three-axis monolithic MEMS accelerometers and methods for fabricating same

A device that includes a substrate with an active region is disclosed. The device includes a gate disposed in the active region and tunable sidewall spacers on sidewalls of the gate. A profile of the tunable sidewall spacers includes upper and lower portions in which width of the spacers in the upper portion is reduced at a greater rate than the lower portion.

Tunable spacers for improved gapfill

A method of fabricating local interconnects of polycide has been achieved. A substrate is provided. Narrowly spaced features, such as MOS transistor gates and polysilicon traces, are provided overlying the substrate. A dielectric layer is deposited overlying the substrate and the narrowly spaced features. The dielectric layer is patterned to form openings between the narrowly spaced features for planned contacts to the surface of the substrate. A doped polysilicon layer is deposited overlying the dielectric layer and filling the openings. The doped polysilicon layer is etched down to the top surface of the narrowly spaced features. The doped polysilicon layer remains in the spaces between the narrowly spaced features. A polycide layer is formed overlying the narrowly spaced features and the doped polysilicon layer. The polycide layer and the doped polysilicon layer are patterned to complete the contacts and create the local interconnects of polycide, and the integrated circuit device is completed.

Method to form polycide local interconnects between narrowly-spaced

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Singapore, Singapore

Ramachandramurthy Pradeep Yelehanka