International Business Machines Corporation

Globalfoundries Inc.

Other

Infineon Technologies Ag

Stmicroelectronics Gmbh

Infineon Technologies North America Corp.

Kabushiki Kaisha Toshiba

Elpis Technologies Inc.

Qimonda Ag

Ramachandra Divakaruni

Kangguo Cheng

Jack Allan Mandelman

Carl John Radens

Gary Bela Bronner

Juntao Li

Jeffrey P Gambino

Ravikumar Ramachandran

Ali Khakifirooz

William R Tonti

Dureseti Chidambarrao

Jeehwan Kim

Ulrike Gruening

Geng Wang

Kern Rim

Jochen C Beintner

Devendra K Sadana

Haining S Yang

James William Adkisson

Johnathan E Faltermeier

Byeong Yeol Kim

Arvind Kumar

Herbert Lei Ho

Henry K Utomo

Russell J Houghton

Bruce Bennett Doris

Edward J Nowak

Xin Miao

Reinaldo Ariel Vega

Viraj Yashawant Sardesai

Alexander Reznicek

Claude Louis Bertin

Arne Watson Ballantine

Soon-Cheon Seo

Michael Patrick Chudzik

Subramanian Srikanteswara Iyer

Wayne Frederick Ellis

Unoh Kwon

Chun-Yung Sung

Theodorus E Standaert

Timothy Joseph Dalton

Dirk Pfeiffer

Bomy A Chen

Siddarth A Krishnan

Randy William Mann

Dae-Gyu Park

Tenko Yamashita

Nicolas J Loubet

Oleg Gluschenkov

Dechao Guo

Ajey Poovannummoottil Jacob

Keith Kwong Hon Wong

Hong He

Jeffrey Bowman Johnson

Thomas W Dyer

Helmut Horst Tews

Emre Alptekin

Richard Anthony Conti

Roger Allen Booth, Jr

Hon-Sum Philip Wong

Michael P Belyansky

Paul Christian Parries

Brent A Anderson

Takashi Ando

Veeraraghavan S Basker

Louis L Hsu

William John Starke

Guy M Cohen

Shogo Mochizuki

Kevin K Chan

Shom Ponoth

Mukta G Farooq

Jed Hickory Rankin

Judson Robert Holt

Cyril Cabral, Jr

Fee Li Lie

Christian Lavoie

Haizhou Yin

Douglas Duane Coolbaugh

Leland Chang

Chung-Hsun Lin

Kevin Shawn Petrarca

Wai-Kin Li

Thomas N Adam

Richard Stephan Wise

Zhengwen O Li

Laertis Economikos

Rolf Weis

John Edward Barth, Jr

Babar Ali Khan

Till Schloesser

Brian Joseph Greene

Wilbur David Pricer

Huiming Bu

Robert C Wong

Joshua M Rubin

Kamal Kumar Sikka

Rajarao Jammy

Fenton Read McFeely

Edward William Kiewra

The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips. Arrays of MCMs and methods of making bridge connects are disclosed. Bridge connector shapes include: rectangular, window pane, plus-shaped, circular shaped, and polygonal-shaped.

Multiple chip bridge connector

A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

Porous silicon relaxation medium for dislocation free CMOS devices

A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.

Third type of metal gate stack for CMOS devices

A plurality of fin structures containing, from bottom to top, a non-doped semiconductor portion and a second doped semiconductor portion of a first conductivity type, extend upwards from a surface of a first doped semiconductor portion of the first conductivity type. A trapping material (e.g., an electron-trapping material) is present along a bottom portion of sidewall surfaces of each non-doped semiconductor portion and on exposed portions of each first doped semiconductor portion. Functional gate structures straddle each fin structure. Metal lines are located above each fin structure and straddle each functional gate structure. Each metal line is orientated perpendicular to each functional gate structure and has a bottommost surface that is in direct physical contact with a portion of a topmost surface of each of the second doped semiconductor portions.

FinFET vertical flash memory

A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.

FinFET with epitaxial source and drain regions and dielectric isolated channel region

A method is presented for forming a semiconductor structure. The method includes forming a bilayer buried insulator over a substrate, forming an extremely thin silicon-on-insulator (ETSOI) over the bilayer buried insulator, forming a dummy gate, and forming a source/drain next to the dummy gate, the source/drain defining a raised source/drain region. The method further includes depositing a dielectric material over the raised source/drain regions, removing the dummy gate to define a recess, implanting a species within a first layer of the bilayer buried insulator, and depositing a gate dielectric and a conducting material within the recess. The method further includes removing the substrate, etching the implanted portion of the first layer of the bilayer buried insulator to expose a surface of a second layer of the bilayer buried insulator, and forming a back gate over the exposed second layer, the back gate self-aligned to the ETSOI channel.

Fully depleted SOI device for reducing parasitic back gate capacitance

A method for forming a semiconductor device includes forming a nanosheet stack comprising alternating layers of a first material and a second material on a substrate. The method further includes removing portions of the stack to form tapered stack sidewalls, which have a taper angle in relation to a horizontal surface of the substrate. The method further includes converting the second material to a resistive material. The layers that include the resistive material form one or more electrical fuses.

Multiple-bit electrical fuses

A semiconductor structure includes a material stack located on a surface of a semiconductor substrate. The material stack includes, from bottom to top, a silicon germanium alloy portion that is substantially relaxed and defect-free and a semiconductor material pillar that is defect-free. A dielectric material structure surrounds sidewalls of the material stack and is present on exposed portions of the semiconductor substrate.

Hybrid aspect ratio trapping

Methods of forming a semiconductor device include forming stress liners in contact with both ends of a fin of alternating channel material and sacrificial material layers. The stress liners exert a stress on the fin. The sacrificial material is etched away from the fin, such that the layers of the channel material are suspended between the stress liners. A gate stack on the suspended layers of channel material.

Integrated strained stacked nanosheet FET

A vertical transistor includes a gate structure interposed between a proximate spacer doped with a first dopant-type and a distal spacer doped with the first dopant-type. The proximate spacer is formed on an upper surface of a semiconductor substrate. At least one channel region extends vertically from the proximate doping source layer to the distal doping source layer. A proximate S/D extension region is adjacent the proximate spacer and a distal S/D extension region is adjacent the distal spacer. The proximate and distal S/D extension regions include dopants that match the first dopant-type of the proximate and distal doping sources.

Vertical transistor including controlled gate length and a self-aligned junction

Transistors include stress liners, with one or more semiconductor structures between the stress liners. The stress liners provide a stress on the one or more semiconductor structures. A gate is formed over and around the one or more semiconductor structures. A source and drain region is formed on the one or more semiconductor structures on opposite sides of the gate, between the stress liners.

A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.

Semiconductor fin isolation by a well trapping fin portion

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Ossining, NY, United States of America

Ramachandra Divakaruni