Texas Instruments Corporation

Rama Venkatasubramanian

Naveen Bhoria

Duc Quang Bui

Dheera Balasubramanian Samudrala

Jose Luis Flores

Alan Davis

Ivan Santos

A digital data processor includes an instruction memory storing instructions specifying a data processing operation and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to perform a table write in response to a look up table initialization instruction by duplicating at least one data element from a source data register to create duplicated data elements, and writing the duplicated data elements to a specified location in a specified number of at least one table and a corresponding location in at least one other table.

Look-up table initialize

A digital data processor includes a multi-stage butterfly network, which is configured to, in response to a look up table read instruction, receive look up table data from an intermediate register, reorder the look up table data based on control signals comprising look up table configuration register data, and write the reordered look up table data to a destination register specified by the look up table read instruction.

Look-up table read

A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to increment histogram values in response to a histogram instruction by incrementing a bin entry at a specified location in a specified number of at least one histogram.

Histogram operation

In described examples, a latch includes active feedback circuitry for latching input information. A comparison of logic states between input and output states at selected times can determine whether, for example, the latch has correctly retained latch data. The latch can optionally be included within a scan chain, provide asynchronous latch error notifications, and/or synchronous notifications indicating where in the scan chain a latch error occurred.

Enhanced fault detection of latched data

An IC includes logic groups each including a launch and a capture FF with a logic cloud in between. A power switch is in series with a power supply node of the logic groups. The logic groups have a clock-gating and power control (PCGC) block for dynamically generating a power supply enable (PS_EN) signal output coupled to a control node of the power switch and a clock output (CLK_OUT) signal coupled to a clock input of the launch or capture FF for clocking the logic groups. The PCGC blocks receive an EN signal and a CLK_IN signal and dynamically generate the PS_EN signal and CLK_OUT signals. During clock cycles at least one logic group(s) does not contribute to an intended logic result for the IC the CLK_OUT signal disables switching of at least a portion of the logic group(s) while the PS_EN signal turns off power to the logic group(s).

Growing community of inventors

Plano, TX, United States of America

Rama Venkatasubramanian