Advanced Micro Devices Corporation

Microelectronics and Computer Technology Corporation

Qualcomm Incorporated

Hughes Aircraft Company

Globalfoundries Inc.

Advance Micro Devices, Inc.

Other

Advanced Mircor Devices, Inc.

Rama Rao Goruganthu

Michael R Bruce

Rosalinda M Ring

Jeffrey David Birdsley

Brennan V Davis

Glen P Gilfeather

Victoria Jean Bruce

Miguel Santana, Jr

Robert Powell

Thomas Chu

Nalin Kumar

Mohammed K Ghazi

Richard W Johnson

Chenggang Xie

Daniel L Stone

Ali Akbar Merrikh

Philip J Spletter

Ronald M Potok

Greg Dabney

Shawn M McBride

Mehdi Saeidi

David Harry Eppes

Damion B Gastelum

Martin L Villafana

Jiann Min Chin

Abdullah Mohamad Yassine

Richard Blish, Ii

Thomas K Myers

Andrew W Ross

Ajay Vadakkepatt

Guoping Xu

Antonio Torres Garcia

Luis Eduardo De Los Heros Beunza

Shannon B Smith

David E Kloster

David Bethke

Gaurav Sunil Mattey

Norman E Rhodes

Aspects of the disclosure are directed to a package including a substrate, die coupled to the substrate, wick deposited on the die, and an evaporation-condensation chamber having a hollowed bottom and two bottom lips, wherein the wick mates into the hollowed enclosure and substantially merges with the two bottom lips forming a sealed chamber. Other aspects are directed to a method of forming a package including coupling a die to a substrate, depositing a wick on the die, and mating the wick with an evaporation-condensation chamber having a hollowed enclosure and two bottom lips, wherein the mating attaches the wick into the hollowed enclosure and substantially merges the wick with the two bottom lips forming a sealed chamber. By directly depositing the wick over the die and integrating the wick with the encapsulation-condensation chamber, this integrated solution provides significant improvement in package thermal resistance especially for high-power and high-performance applications.

High performance evaporation-condensation thermal spreading chamber for compute packages

An apparatus is disclosed that comprises an integrated circuit and a thermal detector array configured to detect thermal radiation from the integrated circuit. A method is disclosed that comprises providing an integrated circuit and disposing a thermal detector array so as to detect thermal radiation from the integrated circuit. Another apparatus is disclosed that comprises means for processing and means for detecting thermal radiation from the means for processing.

Thermal detector array configured to detect thermal radiation from the integrated circuit

A transparent coversheet intervenes between a lens and a thinned die in a visible light fault analysis tool so that the thinned die is robust to fractures. In addition, the transparent coversheet has a greater thermal mass than the thinned die and thus acts as a heat sink to prevent active circuitry in the thinned die from overheating during the visible light fault analysis.

Visible laser circuit fault isolation

The present application discloses various implementations of a laser scanning module. In one implementation, such a laser scanning module comprising an optical isolator including first and second linear polarizers, a collimating optics configured to receive light produced by a laser light source and to pass a substantially collimated light beam to the first linear polarizer, and a scanning unit situated to receive light passed by the second linear polarizer. The first linear polarizer is separated from the collimating optics by a first distance less than a second distance separating the second linear polarizer from the scanning unit.

Laser scanning module including an optical isolator

Various apparatus and methods of testing a semiconductor chip for soft defects are disclosed. In one aspect, a method of testing a semiconductor chip that has a surface and plural circuit structures positioned beneath the surface is provided. An irradiation mask directs light or heat to a series of fractional portions of the surface to perturb portions of the plural circuit structures. The irradiation mask is adjustable such that at least one of the exposed series of fractional portions is smaller than another of the series of fractional portions. The semiconductor chip undergoes a test pattern during the irradiation to each of the fractional portions to determine if a soft defect exists in any of the series of fractional portions. Multiple paths can be tested simultaneously to inform subsequent individual CTP path tests.

Wide area soft defect localization

According to one embodiment, an optical isolation module includes first and second linear polarizers, a Faraday rotator situated between the first and second linear polarizers and a transmissive element including a half-wave plate also situated between the first and second linear polarizers. In one embodiment, a method for performing optical isolation includes rotating an axis of polarization of a linearly polarized light beam by a first rotation in a first direction, and selectively rotating a portion of the linearly polarized light beam by a second rotation in the first direction to produce first and second linearly polarized light beam portions. As a result, the first linearly polarized light beam portion undergoes the first rotation, and the second linearly polarized light beam portion undergoes the first and second rotations. The method further includes filtering one of the first and second linearly polarized light beam portions to produce a light annulus.

Optical isolation module and method for utilizing the same

A silicon photon detector device and methodology are provided for detecting incident photons in a partially depleted floating body SOI field-effect transistor () which traps charges created by visible and mid infrared light in a floating body region () when the silicon photon detector is configured in a detect mode, and then measures or reads the resulting enhanced drain current with a current detector in a read mode.

Silicon photon detector

Lithography using solid immersion lenses is disclosed. In one aspect, an apparatus is provided that includes a resist film that has a first side and a second and opposite side. One or more solid immersion lenses are positioned over the first side of the resist film. In another aspect, a method of manufacturing is provided that includes forming a resist film and exposing the resist film with radiation transmitted through one or more solid immersion lenses.

Solid immersion lens lithography

Various apparatus and methods of testing a semiconductor chip for soft defects are disclosed. In one aspect, a method of testing a semiconductor chip that has a surface and plural circuit structures positioned beneath the surface is provided. An external stimulus is applied to a series of fractional portions of the surface to perturb portions of the plural circuit structures such that at least one of the series of fractional portions is smaller than another of the series of fractional portions. The semiconductor chip is caused to perform a test pattern during the application of external stimulus to each of the fractional portions to determine if a soft defect exists in any of the series of fractional portions.

Various devices for mounting circuit devices and methods of making the same are provided. In aspect, a device is provided that includes a member for holding an integrated circuit. The member contains a first plurality of carbon nanotubes to enhance the thermal conductivity thereof. At least one conductor member projects from the member. In another aspect, a method of fabricating an interface for an electronic component is provided that includes forming a member containing a first plurality of carbon nanotubes and forming at least one conductor on the member.

Thermally conductive integrated circuit mounting structures

Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by accessing the circuitry within the die from the back side without necessarily breaching or needing to breach the thin insulator layer of the SOI structure. According to an example embodiment of the present invention, a portion of substrate is removed from the back side of a semiconductor die having a SOI structure and a backside opposite circuitry in a circuit side. An exposed region is formed where the substrate has been removed. A detectable response from the exposed region is induced, for example, by an electron beam, as a function of a portion of the active circuitry within the die.

Electrical probing of SOI circuits

A light reflected from a semiconductor die is used for enhanced control of substrate removal from the die. According to an example embodiment of the present invention, light reflected from a semiconductor die as it is undergoing substrate removal is used to detect the progress of the substrate removal process, and the removal process is controlled therefrom. In different embodiments, the reflected light is used to detect the removal of a portion of a layer of material in the die and to detect the removal of an entire layer of material.

Semiconductor die analysis as a function of optical reflections from the die

According to one aspect of the disclosure and a particular example application directed to a flip-chip packaged die, a method for detecting a defect in a surface of the die includes directing light through a first beam splitter; directing light of a known wavelength at the beam splitter, wherein the first beam splitter is adapted to direct a first beam of light into the back side of the semiconductor die which reflects a second beam of light back; and redirecting the second beam to a second beam splitter, the second beam splitter generating third and fourth beams of light. Analysis of the third and fourth beams of light is then performed, and this analysis can include using detectors in respective paths of the third and fourth beams of light to generate an arrival time differential and then comparing the differential with a reference previously generated using a nondefective die.

Dual-differential interferometry for silicon device damage detection

Circuitry within a semiconductor die is analyzed by applying an electric field without necessarily directly accessing the circuitry. According to an example embodiment of the present invention, an electric field is applied to a semiconductor die and used to stimulate circuitry therein. A photoemission response of the die to the electric field is detected and used to detect an electrical characteristic of the die. This is particularly useful in applications where it is desired to direct stimulation to the die from an external source and to also externally detect a response of the die to the stimulation. In this manner, the die can be tested without necessarily directly contacting the die and, when the electric field is applied in a scanning mode over the die, can be effected without necessarily knowing the location of a defect in the die.

Circuit analysis and manufacture using electric field-induced effects

Growing community of inventors

Austin, TX, United States of America

Rama Rao Goruganthu