International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

The Perkin-elmer Corporation

Rama Nand Singh

Fuad Elias Doany

Fook-Luen Heng

George L Chiu

Janusz S Wilczynski

Thomas Mario Cipolla

Mark Alan Lavin

Alan Edward Rosenbluth

Derek Brian Dove

Evan G Colgan

Kafai Lai

Jin Fuw Lee

Lars W Liebmann

Masaru Suzuki

John Maxwell Cohn

James A Culp

Ulrich Alfons Finkler

Gregory Allen Northrop

Leon Stok

Jin-Fuw Lee

Nakgeuon Seong

Rajiv V Joshi

John Peter Karidis

Russell Alan Budd

Yoichi Taira

Ioana C Graur

Kehan Tian

Saeed Reza Bagheri

David Osmond Melville

Jawahar P Nayak

Chieh-Yu Lin

Saibal Mukhopadhyay

Pieter J Woeltgens

Dureseti Chidambarrao

Maharaj Mukherjee

David R Shafer

Robert L Wisnieff

Hon-Sum Philip Wong

Satoshi Maruyama

Amith Singhee

Emrah Acar

Fumiaki Yamada

Geng Han

Dale J Pearson

Aditya Bansal

Donald J Samuels

Robert Lee Melcher

Jungwook Yang

Sudhir Muniswamy Gowda

Akiko Nishikai

Zachary Baum

Abe Offner

Hideo Ohkuma

Yuping Cui

Roger Y Tsai

Chao Yi Tien, Legal Representative

Pieter J Woltgens

Zhong John Deng

Tomohito Jounai

Thomas Ainsworth, Jr

Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.

Analyzing a patterning process using a model of yield

Techniques for generating variants of a circuit layout and evaluating quality of the variants are provided. In one aspect, a method for generating at least one variant layout for a cell design includes the following steps. At least a first basis layout and a second basis layout are obtained for the cell design, each having a plurality of shapes, each of the shapes being a polygon having a plurality of sides and vertices. One or more of the shapes in the first basis layout are linked with one or more of the shapes in the second basis layout that represent a common feature of the cell design resulting in a plurality of linked shapes. Starting with either the first basis layout or the second basis layout, a location of the vertices of each of the linked shapes are changed to produce the variant layout for the cell design.

Performance driven layout optimization using morphing of a basis set of representative layouts

A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Physical design system and method

A method of physical design for integrated circuit (IC) chip fabrication, physical design system and program product therefor. A design shape is fragmented into segments for Optical Proximity Correction (OPC) and a harmonic mean of the segments is determined. Electrical intent is determined for the shape and a harmonic mean is determined for the segments. Segments may be moved based on a effect on the harmonic mean from moving the segments, measured using a harmonic mean cost function. Finally segmented shapes are passed to OPC.

Optimizing integrated circuit chip designs for optical proximity correction

A system and method of employing patterning process statistics to evaluate layouts for intersect area analysis includes applying Optical Proximity Correction (OPC) to the layout, simulating images formed by the mask and applying patterning process variation distributions to influence and determine corrective actions taken to improve and optimize the rules for compliance by the layout. The process variation distributions are mapped to an intersect area distribution by creating a histogram based upon a plurality of processes for an intersect area. The intersect area is analyzed using the histogram to provide ground rule waivers and optimization.

System and method for employing patterning process statistics for ground rules waivers and optimization

A method for predicting functionality of an integrated circuit segment to be lithographically printed on a wafer. Initially there is provided a two-dimensional design of an integrated circuit, including an integrated circuit segment having critical width, and a two-dimensional printed image of the critical width integrated circuit segment is simulated. The method then includes determining a ratio of perimeters or areas of the designed critical width integrated circuit segment to the simulated printed critical width integrated circuit segment, and predicting functionality of the critical width integrated circuit segment after printing based on the ratio of perimeters or areas.

Methodology for image fidelity verification

A methodology for obtaining improved prediction of CA resistance in electronic circuits and, particularly, an improved CA resistance model adapted to capture larger than anticipated 'out of spec' regime. In one embodiment, a novel bucketization scheme is implemented that is codified to provide a circuit designer with considerably better design options for handling large CA variability as seen through the design manual. The tools developed for modeling the impact of CA variable resistance phenomena provide developers with a resistance model, such as conventionally known, modified with a new CA model Basis including a novel CA intrinsic resistance model, and, a novel CA layout bucketization model.

CA resistance variability prediction methodology

A method of designing lithographic masks is provided where mask segments used in a model-based optical proximity correction (MBOPC) scheme are adaptively refined based on local image information, such as image intensity, gradient and curvature. The values of intensity, gradient and curvature are evaluated locally at predetermined evaluation points associated with each segment. An estimate of the image intensity between the local evaluation points is preferably obtained by curve fitting based only on values at the evaluation points. The decision to refine a segment is based on the deviation of the simulated image threshold contour from the target image threshold contour. The output mask layout will provide an image having improved fit to the target image, without a significant increase in computation cost.

Method for adaptive segment refinement in optical proximity correction

A method of verifying the placement of sub-resolution assist features (SRAFs) in a photomask layout is described. SRAFs are added to the photomask layout to enhance the process window for semi-isolated and isolated features. Rules are provided to automatically place the SRAFs into the layout. When deficiencies are detected in the assist feature design or in the automated SRAF placement program, the placement of SRAFs requires verification. The method verifies the correct placement by defining a unique image property linked to the accurate placement of the assist features, and combines it with in-situ image simulation of the individual layout. The placement of the SRAFs is verified by: 1) formulating a unique image property using a technology specific representative sample design with and without properly placed SRAFs; 2) simulating the resist image of each individual device layout in the photomask, considering the layout environment of each individual device, and analyzing the unique image properties associated with the device being examined; 3) sorting the geometric properties of each device into predetermined category; and 4) for each individual device layout, examining the image property value and geometric category values, and determining whether the device is adequately surrounded by SRAFs. If not, individual device on the photomask layout are marked with error marker shapes to be subsequently corrected.

Method of verifying the placement of sub-resolution assist features in a photomask layout

An image capture system for mobile communications systems includes an imaging device for capturing optical image data and a data transfer apparatus coupled to a communications device communications device for transferring the optical image data to the communications device for transmittal over a communications network.

Image capture system for mobile communications

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Bethel, CT, United States of America

Rama Nand Singh