National Semiconductor Corporation

Ram Veeraraghavan

Anindya Poddar

Shaw Wei Lee

Thanh Lequang

A variety of improved substrate structures and substrate fabrication techniques for use in integrated circuit packaging are described. In one aspect, a substrate strip fabrication technique that facilitates strip testing of the dice mounted thereon is described. The described technique works well even when landings on the substrate are electrolytically plated. In a preferred embodiment, the substrate is formed in a manner that facilitates the use of non-stick detection during wire bonding. In a distinct aspect of the invention the substrate strip has a plurality of distinct molding area tiles that each have a two dimensional array of substrate segments formed thereon. The substrate segments each have a die attach area, a plurality of landing one surface and a plurality of contact pads on the other. The contact pads are positioned substantially across from the landings and are electrically connected thereto by associated vias. The landings have bond pads suitable for use in wire bonding and are preferably arranged in at least one row that extends adjacent or around the die attach area. The contact pads are positioned opposite the landings. With this arrangement, extended routing traces are not required to electrically couple the bond pads to the contact pads.

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Singapore, Singapore

Ram Veeraraghavan