International Business Machines Corporation

Ram Sai Manoj Bamdhamravuri

Craig Raymond Walters

Alper Buyuktosunoglu

Deanna Postles Dunn Berger

Dominic Ditomaso

Robert J Sonnelitter, Iii

Gregory William Alexander

Timothy Carl Bronson

Kenneth Douglas Klapproth

Guy G Tracy

David Trilla Rodriguez

Christian Jacobi

Ulrich Mayer

Hieu Trong Huynh

Deanna P Berger

Mark R Hodges

Jason D Kohl

Deanna P D Berger

Chad G Wilson

Richard Joseph Branciforte

Avery Francois

Chunggeon Rhee

Robert Sonnelitter

Processing within a computing environment is facilitated by using cache hit-miss predictions. A cache hit-miss prediction is determined for a memory access instruction using a predictor. One or more speculative actions are controlled, based on determining the cache hit-miss prediction is a miss. The controlling is further based on a type of cache design.

Controlling speculative actions based on a hit/miss predictor

Examples described herein provide a computer-implemented method that includes generating an extended hot line table that tracks cross-core contended cache lines for multiple processors of a processing system based on cache requests, the extended hot line table storing at least metadata for a cross-core contended cache line. The method further includes polling, using firmware, the extended hot line table in each of the multiple processors of the processing system to identify contention information. The method further includes aggregating the contention information from each of the multiple processors to generate aggregated contention information. The method further includes processing subsequent cache requests using the aggregated contention information.

Detecting and mitigating false structure sharing within a cache line

A cache hit-miss prediction is determined for a memory access instruction using a predictor. The predictor includes a tracker for the memory access instruction. The tracker is used to provide a prediction confidence level of the cache hit-miss prediction for the memory access instruction. Using the tracker, the prediction confidence level of the cache hit-miss prediction is ascertained. Based on the prediction confidence level indicating the cache hit-miss prediction is to be used, the cache hit-miss prediction is provided to be used in instruction execution scheduling.

Instruction execution scheduling using a hit/miss predictor

A computer system and a method implementing a remote access array are provided. A first drawer includes a first processor chip. A first main memory region is operatively connected to the first processor chip. A first non-addressable memory region is operatively connected to the first processor chip and includes the first remote access array. The first remote access array is configured to track data portions that are stored in the first main memory region and for which copies were created and sent to an external node. The first remote access array is backed up in the first main memory region. The first remote access array includes one or more entries and is configured to update all of the entries in response to a multi-drawer working partition being reduced to fit within the first drawer.

Remote access array

Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

Lateral persistence directory states

Aspects of the invention include computer-implemented methods, systems, and computer program products that access a multi-copy scope directory state of a cache memory that indicates a scope of sharing of a cache line in a cache memory system and determine a scope of sharing of the cache line in the cache memory system based on the multi-copy scope directory state, where the multi-copy scope directory state enumerates a plurality of scopes within the cache memory system. The scope of sharing is used to reduce a number of queries to one or more cache memories having a larger scope than a shared scope identified in the scope of sharing. The multi-copy scope directory state of the cache memory is updated based on detecting a change in shared scope of the cache line within the cache memory system.

Multiple copy scoping bits for cache memory

Methods, systems and computer program products for measuring hardware performance are provided. Aspects include receiving an indication of a start to a hardware operation. A number of clock cycles are counted from the start of a hardware operation to the completion of the hardware operation. A first region comprising a first set of bit location is defined. A second and third region is defined each including a set of bit locations. Based on the first set of bit locations being equal to zero, a granularity flag is set to zero in the sample buffer and the second and third set of bit locations are written to the sample buffer. And based on the first set of bit locations being greater than zero, the granularity flag in the sample buffer is set to one and the first and second set of bit locations are written to the sample buffer.

Accuracy sensitive performance counters

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Poughkeepsie, NY, United States of America

Ram Sai Manoj Bamdhamravuri