Intel Corporation

Ram Livne

Ariel Cohen

Yoel Krupnik

Ahmad B Khairi

Roee Eitan

Dror Lazar

Vladislav Tsirkin

Adee Ofir Ran

Ronald W Swartz

Ro'ee Eitan

Tomer Fael

Alexander Pogrebinsky

Ilya Kraimer

Hen Sallem

Idan Lotan

Yosi Sanhedrai

A comparator is described. The comparator includes a differential pair having first and second transistors to respectively receive first and second input signals. The comparator also includes a current sink or source transistor coupled to respective source nodes of the first and second transistors. The current sink or source transistor is coupled to receive a fixed bias to keep the current sink transistor active so that large voltage changes on the source nodes is avoided. The comparator circuit includes a latch circuit coupled to respective drain nodes of the first and second transistors. The latch circuit is to reach a final state to present the comparator's output signal. The comparator includes a first switch circuit coupled between the first transistor's drain node and the latch circuit, and a second switch circuit coupled between the second transistor's drain node and the latch circuit. The first and second switch circuits to allow the first and second transistors' respective drain node voltage and source node voltage to enter and exit the comparator's comparison state at a same voltage.

High-speed, low power, low kickback noise comparator suitable for a multi-comparator successive approximation analog-to-digital converter (ADC)

An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.

Analog to digital convertor (ADC) using a common input stage and multiple parallel comparators

One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.

Slicer and decision feedback equalization circuitry

A method and system to facilitate configurable input/output (I/O) termination voltage reference in a transmitter or receiver. In one embodiment of the invention, the transmitter and receiver, each has a termination circuit to select a suitable termination reference voltage based on the desired coupling type. In one embodiment of the invention, the transmitter has a termination circuit coupled with a transmission driver and the transmitter selects only one of a supply voltage, a ground voltage and a half supply voltage as a termination voltage reference of the transmission driver. The receiver has a termination circuit to select either a supply voltage or a ground voltage as a termination voltage reference of the receiver.

Method and system to facilitate configurable input/output (I/O) termination voltage reference

Growing community of inventors

Ramat Raziel, Israel

Ram Livne