International Business Machines Corporation

Globalfoundries Inc.

Ram Kelkar

Anjali R Malladi

John S Austin

Pradeep Thiagarajan

Stephen Dale Wyatt

Ilya I Novof

Ramana Murty Malladi

Herschel Akiba Ainspan

Hayden C Cranford, Jr

Martin L Schmatz

Joseph Andrew Iadanza

Anthony Richard Bonaccio

Grant Paul Kesselring

Zhenrong Jin

Jeffery Howard Oppold

Faraydon Pakbaz

Donald E Strayer

Richard F Keil

Kenneth Dean Short

Iiya I Novof

Nina A Shah

Variable capacitor structures and methods of use are disclosed. The variable capacitor structures include a variable controlled oscillator which includes a variable capacitor structure having at least one capacitor set driven by a control gate voltage of a voltage control circuit which comprises a logic cell that senses a selected frequency band and sets the control gate voltage based on the selected frequency band.

Variable capacitor structure

Embodiments of the present invention provide a design structure and method for compensating for a change in frequency of oscillation (FOO) of an LC-tank VCO that includes a first node; second node; inductor; first capacitive network (FCN) that allows the design structure to obtain a target FOO; compensating capacitive (CCN) network that compensates for a change in the design structure's FOO; second capacitive network (SCN) that allows the design structure to obtain a desired FOO; a filter that supplies a voltage to the SCN and is coupled to the SCN; a transconductor that compensates for a change in the design structure's FOO; and a sub-circuit coupled to the SCN that generates and supplies voltage to the CCN sufficient to allow the CCN to compensate for a reduction in the design structure's FOO. The first and second nodes are coupled to the inductor, FCN, CCN, SCN, and sub-circuit.

Structure for an inductor-capacitor voltage-controlled oscillator

An approach for a transconductance cell for use in a voltage controlled oscillator (VCO) is provided. The transconductance cell includes a first NFET stack connected in series to a first PFET stack. The transconductance cell includes a second NFET stack connected in series to a second PFET stack. The first NFET stack and the first PFET stack are cross-coupled to the second NFET stack and the second PFET stack. The first NFET stack and the second NFET stack are connected to a tail node. The first PFET stack and the second PFET stack are connected to a power supply node.

Phase noise reduction in LC-VCO

An input jitter filter for a phase-locked loop and methods of use are provided. The method includes generating a masking zone around falling edges of a feedback signal. The method also includes determining that one or more outputs of a phase detector fall within the masking zone. The method further includes ignoring input clock noise when the one or more outputs of the phase detector fall within the masking zone.

Input jitter filter for a phase-locked loop (PLL)

A programmable filter for LC tank voltage controlled oscillator (VCO) and a design structure for a programmable filter for LC tank VCO. The programmable filter includes a proportional control comprising a plurality of capacitance biased by different input voltages and an integral control comprising a filter element with a capacitance Cand a set of capacitance biased by a voltage output of the filter element.

Programmable filter for LC tank voltage controlled oscillator (VCO), design structure and method thereof

A current controlled, phase locked loop device includes a phase detector configured to compare a reference frequency to an output frequency of a current controlled oscillator (ICO), a charge pump coupled to the phase detector and a low pass filter coupled to the charge pump. A voltage to current (V to I) converter is coupled to the low pass filter, providing an output current for integral control of the ICO. A control circuit is coupled to the ICO, and receives increment and decrement outputs of the phase detector, wherein the control circuit is configured to provide proportional control of the ICO through an amount of bias current applied thereto.

Current controlled oscillation device and method having wide frequency range

An oscillation circuit and the method for operating the same. The circuit includes (a) an LC oscillator including an inductor and a variable capacitor; (b) first and second differentially-coupled transistors (i) electrically coupled to the LC oscillator and (ii) configured to provide negative resistance to the LC oscillator; and (c) a first current-injecting circuit (i) electrically coupled to the first differentially-coupled transistor and (ii) configured to inject a first additional electric current into the first differentially-coupled transistor so as to cause the first differentially-coupled transistor to create a first additional negative resistance to the LC oscillator; and (d) a second current-injecting circuit (i) electrically coupled to the second differentially-coupled transistor and (ii) configured to inject a second additional electric current into the second differentially-coupled transistor so as to cause the second differentially-coupled transistor to create a second additional negative resistance to the LC oscillator.

Negative resistance oscillator with additional bias current injection

A design structure embodied in a machine readable medium used in a design process includes a current controlled, phase locked loop device having a phase detector configured to compare a reference frequency to an output frequency of a current controlled oscillator (ICO), a charge pump coupled to the phase detector and a low pass filter coupled to the charge pump. A voltage to current (V to I) converter is coupled to the low pass filter, providing an output current for integral control of the ICO. A control circuit is coupled to the ICO, and receives increment and decrement outputs of the phase detector, wherein the control circuit is configured to provide proportional control of the ICO through an amount of bias current applied thereto.

Design structure for improved current controlled oscillation device and method having wide frequency range

A method for dividing a high-frequency signal. The method including: generating, from a first clock signal, a second clock signal, the second clock cycle time greater than the first clock cycle time, an off-time of one cycle of the second clock signal being one first clock cycle time less than an on-time of one cycle of the second clock signal; shifting in time the second clock signal by half of a first clock cycle time to generate a third clock signal, the second clock cycle time equal to the third clock cycle time; performing a logical AND of the second clock signal and the third clock signal to generate a fourth clock signal, the third clock cycle time equal to the fourth clock cycle time, an on-time of one cycle of the fourth clock signal equal to an off-time of one cycle of the fourth clock signal.

Method for dividing a high-frequency signal

A frequency coincidence detection circuit for detecting frequency edges for each of a plurality of periodic digital signals. The circuit generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The circuit determines a signal coincidence of the coincidence windows. In another embodiment, a frequency coincidence detection method is provided. The method detects frequency edges for each of a plurality of periodic digital signals, generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The method determines a signal coincidence of the coincidence windows.

Programmable sensitivity frequency coincidence detection circuit and method

Disclosed are design structures for systems and methods of generating a periodic signal.

Structure for voltage controlled oscillator

Jitter method and control circuit for a circuit block in a transceiver system having a phase lock loop circuit which includes an oscillator, a charge pump connected to the oscillator to add or subtract charge to or from said oscillator, and a low pass filter connected to said charge pump are provided. Circuitry is connected to the output of the oscillator and the input of the charge pump to control the amount of charge added to or subtracted from the charge pump to control the bandwidth output by the oscillator and thereby reduce jitter in the phase lock circuit.

Adjustment of PLL bandwidth for jitter control using feedback circuitry

Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.

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South Burlington, VT, United States of America

Ram Kelkar