Intel Corporation

Marvell International Limited

Carnegie Mellon University

Ram K Krishnamurthy

Steven Hsu

Gregory Kengho Chen

Sanu K Mathew

Phil Knag

Huseyin Ekin Sumbul

Raghavan Kumar

Amit Agarwal

Mark A Anders

Abhishek A Sharma

Sasikanth Manipatruni

Ian A Young

Amrita Mathuriya

Atila Alvandpour

Himanshu Kaul

Simeon Realov

Krishnamurthy Soumyanath

Van H Le

Sudhir K Satpathy

Vivek K De

Victor W Lee

Farhana Sheikh

Siva G Narendra

Shay Gueron

Atul Maheshwari

Bhaskar P Chatterjee

Jack T Kavalieros

Michael E Kounavis

Hui Jae Yoo

Iqbal Rajwani

Satish K Damaraju

Jesse R Walker

Jiangtao Li

Anand Rajan

Soumyanath Krishnamurthy

Rajaraman Ramanarayanan

Chris Hyung-il Kim

Peter Caputa

Muhammad M Khellah

Uygar E Avci

Noriyuki Sato

Tanay Karnik

James W Tschanz

Shih-Lien L Lu

Ernie F Brickell

Ganesh Balamurugan

Nazila Haratipour

Patrick Koeberl

Mahesh K Kumashikar

Manoj Sinha

Sarah Atanasov

Vasantha K Erraguntla

Roel Maes

Maged Ghoneima

Yehea I Ismail

Monodeep Kar

Sanu K Matthew

Yiben Ye

Per Larsson-Edefors

Rajamohana Hegde

Lei Wang

Ravi Pillarisetty

Vinodh Gopal

Dmitri E Nikonov

Dinesh Somasekhar

Kevin Lai Lin

Mauro J Kobrinsky

Shekhar Yeshwant Borkar

Peter Hazucha

Ali Keshavarzi

Gautham N Chinya

Vikram B Suresh

Men Long

Sriram R Vangal

William C Hasenplaugh

Jae-sun Seo

Alpa T Narendra Trivedi

L Richard Carley

Manoj Sachdev

Anupama Ambardar Thaploo

Rachael Jade Parker

Suresh Srinivasan

Huichu Liu

Sapumal Wijeratne

Zheng Guo

Hossein Alavi

Arnab Raha

Debabrata Mohapatra

Sarvesh H Kulkarni

Herman Henry Schmit

Feroze Merchant

Randy L Allmon

Reed D Spotten

Yejoong Kim

Vinod Sannareddy

Gian Gerosa

Jonathan Enoch

Vishak Venkatraman

Daniel I Davis

Hoang Q Dao

Systems, apparatuses and methods identify a plurality of registers that are associated with a system-on-chip. The plurality of registers includes a first portion dedicated to write operations and a second portion dedicated to read operations. The technology writes data to the first portion of the plurality of registers, and transfers the data from the first portion to the second portion.

Multi-buffered register files with shared access circuits

An apparatus is described. The apparatus includes a long short term memory (LSTM) circuit having a multiply accumulate circuit (MAC). The MAC circuit has circuitry to rely on a stored product term rather than explicitly perform a multiplication operation to determine the product term if an accumulation of differences between consecutive, preceding input values has not reached a threshold.

LSTM circuit with selective input computation

Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a first height, and a second interconnect disposed in the ILD, wherein the second interconnect has a second height that is different than the first height.

Multi-height interconnect trenches for resistance and capacitance optimization

A method comprising: dividing a 3D space into a voxel grid comprising a plurality of voxels; associating a plurality of distance values with the plurality of voxels, each distance value based on a distance to a boundary of an object; selecting an approximate interpolation mode for stepping a ray through a first one or more voxels of the 3D space responsive to the first one or more voxels having distance values greater than a threshold; and detecting the ray reaching a second one or more voxels having distance values less than the first threshold; and responsively selecting a precise interpolation mode for stepping the ray through the second one or more voxels.

Apparatus and method for approximate trilinear interpolation for scene reconstruction

Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

Compute near memory with backend memory

A parasitic-aware single-edge triggered flip-flop reduces clock power through layout optimization, enabled through process-circuit co-optimization. The static pass-gate master-slave flip-flop utilizes novel layout optimization enabling significant power reduction. The layout removes the clock poly over notches in the diffusion area. Poly lines implement clock nodes. The poly lines are aligned between n-type and p-type active regions.

Low power flip-flop with reduced parasitic capacitance

A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

High performance fast Mux-D scan flip-flop

Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a FinFET transistor and a RRAM storage cell. The FinFET transistor includes a fin structure on a substrate, where the fin structure includes a channel region, a source region, and a drain region. An epitaxial layer is around the source region or the drain region. A RRAM storage stack is wrapped around a surface of the epitaxial layer. The RRAM storage stack includes a resistive switching material layer in contact and wrapped around the surface of the epitaxial layer, and a contact electrode in contact and wrapped around a surface of the resistive switching material layer. The epitaxial layer, the resistive switching material layer, and the contact electrode form a RRAM storage cell. Other embodiments may be described and/or claimed.

FinFET transistor based resistive random access memory

An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits

A compute near memory (CNM) convolution accelerator enables a convolutional neural network (CNN) to use dedicated acceleration to achieve efficient in-place convolution operations with less impact on memory and energy consumption. A 2D convolution operation is reformulated as 1D row-wise convolution. The 1D row-wise convolution enables the CNM convolution accelerator to process input activations row-by-row, while using the weights one-by-one. Lightweight access circuits provide the ability to stream both weights and input rows as vectors to MAC units, which in turn enables modules of the CNM convolution accelerator to implement convolution for both [1&#xd7;1] and chosen [n&#xd7;n] sized filters.

Compute near memory convolution accelerator

An apparatus is formed. The apparatus includes a stack of semiconductor chips. The stack of semiconductor chips includes a logic chip and a memory stack, wherein, the logic chip includes at least one of a GPU and CPU. The apparatus also includes a semiconductor chip substrate. The stack of semiconductor chips are mounted on the semiconductor chip substrate. At least one other logic chip is mounted on the semiconductor chip substrate. The semiconductor chip substrate includes wiring to interconnect the stack of semiconductor chips to the at least one other logic chip.

Multi-chip module having a stacked logic chip and memory stack

An apparatus is described. The apparatus includes a circuit to process a binary neural network. The circuit includes an array of processing cores, wherein, processing cores of the array of processing cores are to process different respective areas of a weight matrix of the binary neural network. The processing cores each include add circuitry to add only those weights of an i layer of the binary neural network that are to be effectively multiplied by a non zero nodal output of an i&#x2212;1 layer of the binary neural network.

Processor array for processing sparse binary neural networks

Examples described herein relate to a neural network whose weights from a matrix are selected from a set of weights stored in a memory on-chip with a processing engine for generating multiply and carry operations. The number of weights in the set of weights stored in the memory can be less than a number of weights in the matrix thereby reducing an amount of memory used to store weights in a matrix. The weights in the memory can be generated in training using gradients from back propagation. Weights in the memory can be selected using a tabulation hash calculation on entries in a table.

Reconfigurable memory compression techniques for deep neural networks

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Beaverton, OR, United States of America

Ram K Krishnamurthy