Zoran Corporation

Ram B Friedlander

Peter Feldman

Alexander Genusov

Vlad Fruchter

Ricardo Jaliff

Rafi Retter

Asaf Mohr

A concurrent vector signal processor includes a resource manager for utilization of captive signal processing resources. The first instructions in a temporary instruction queue are predecoded and the signal processing resources are selected to execute those first instructions. Arbitration system is provided for external buses connected to a concurrent vector signal processor. A processor arbiter supervises on a priority basis both captive processor resources and independent processor resources. A bus arbiter supervises on a priority basis external and internal buses.

Bus arbitration and resource management for concurrent vector signal

Multiple special purpose processing units are provided in a vector signal processor for concurrent, parallel processing, particularly of complex vectors. The principal processing units are an execution unit, a data movement unit, a control/register unit, a vector buffer unit, an instruction fetch unit, and a bus interface unit.

Architecture for integrated concurrent vector signal processor

An arithmetic unit for a vector signal processor implements IEEE Standard 754 for Floating-Point Arithmetic. The arithmetic unit includes three pipelined floating-point computational blocks: a multiplier, an adder-subtracter, and an adder to provide for high computation throughput for digital signal processing (DSP) operations. The adder-subtracter and the adder have the same input operands, so that the sum and difference of these input operands can be computed simultaneously. A first and a second internal data bus are provided for transferring data and instructions within the arithmetic execution unit. The input/output operands and partial results are stored in a set of auxiliary registers. Most of these registers can be organized in pairs that for complex arithmetic computations are used to store the real and the imaginary parts of a complex operand. A register-pair can also simultaneously handle two different real operands. The operands are fetched from an internal data buffer from, for example, sources internal to the integrated circuit such as internal RAM, ROM and arithmetic registers. Computation results from the Multiplier, the Adder, and the Adder-Subtracter are temporary stored in the auxiliary registers before writing to the internal RAM or arithmetic registers of the integrated circuit. Data-flow in the vector arithmetic unit is controlled by a vector control unit.

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Haifa, Israel

Ram B Friedlander