National Semiconductor Corporation

Infineon Technologies Ag

Ralph W Haines

Klaus Oberlaender

Thomas W Thomson

Gary D Phillips

Eric John Chesters

D Kevin Covey

Dirk Behrens

Robert James Divivier

Mario D Nemirovsky

Alexander Perez

A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.

Configurable embedded processor

An embedded processor architecture includes a processing core with configurable memory system. Memory components can be inserted, omitted and resized in different configuration of the memory system without causing irregular features that may cause wasted silicon area. Furthermore, all the various configurations of the memory system are designed to interface with the processing core so that the processing core can be reused without change.

Configurable memory system for embedded processors

Memory requests are pipelined to an external memory by forming a memory address during the same clock cycle that the associated instruction is executed, issuing a ready signal during the clock cycle that precedes the clock cycle in which information is output from an external memory, and directing information received from the external memory to a register file during the same clock cycle that the information is received. In addition, when an instruction requires the information that was requested by the previous instruction, the information is directed to an arithmetic logic unit (ALU) during the same clock cycle that the information is received. As a result, the cycle time required to retrieve information stored in a DRAM can be substantially reduced.

Pipelined microprocessor that pipelines memory requests to an external

An arithmetic unit for multiplying and accumulating signed binary data and indicating an occurrence of a signed arithmetic overflow includes a multiplier-accumulator and an overflow flag register. The multiplier-accumulator receives and selectively multiples and accumulates signed binary data, and provides output data representing the multiplied and accumulated data and a sign bit representing its polarity, i.e. positive or negative. The flag register provides two 'sticky' flag bits for indicating whether a signed arithmetic overflow (positive or negative) of the multiplied and accumulated data has occurred. The flag bits are 'sticky' in that once a flag has been set, it cannot be reset by another arithmetic overflow condition. Instead, it must be specifically reset. The sign bit is used to selectively set one of the two sticky flag bits to a true state to indicate the direction (positive or negative) of the first arithmetic overflow. The sticky flag bits have mutually exclusive true states in that once a flag bit has been set true, the other flag bit cannot be set true until both flag bits have been specifically reset.

Signed overflow sticky bits

An integrated circuit (IC) processor architecture is disclosed that implements hardware, signal processing (DSP) functions with less digital improved speed and a more efficient layout. The resources of the central processing unit (CPU) are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Internal registers of the CPU are used to store pointers which reference a circular sample buffer. The CPU thus manages the selection and transfer of coefficients from the sample buffer to the multiply/accumulate unit, thereby allowing a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permitting DSP operations to be performed in parallel with CPU operations.

CPU with integrated multiply/accumulate unit

An integrated circuit processor architecture that implements digital signal processing (DSP) functions with less hardware, improved speed and a more efficient layout. The central processing unit (CPU) resources are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Use of the CPU's internal register for the circular buffer of the DSP multiply/accumulate function allows a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permits DSP operations to be performed in parallel. The multiply/accumulate unit takes advantage of the inherent accumulating properties of conventional multiplier designs to perform multiplication of two signed binary numbers using the modified Booth's algorithm but in both reduced cycle time and hardware requirements. This is accomplished by using the adder within the multiplier to sum the product terms. Instead of clearing the adder of the result of one multiplication before beginning another, the result is maintained and all subsequent partial products are added to it to generate a final output. The placement of the 32-bits of the multiply/accumulate unit's multiplicand register is arranged in two rows of 8 even bits and two rows of 8 odd bits to allow left shift by two with a single loop around and to provide direct interface with the 16-bit data latch register on its input and the rest of the 32-bit arithmetic logic unit (ALU) on its output.

Layout efficient 32-bit shifter/register with 16-bit interface

An I/O control circuit is provided which is of the type that receives two inputs such that four sets of input conditions to the circuit are defined. A first set of input conditions establishes a low impedance path from the circuit output to the positive supply. A second set of input conditions establishes a low impedance path from the output to the negative supply, or ground. A third set of input conditions establishes a high impedance path from the output to both the positive and the negative supply. And, in accordance with the present invention, 'pull-up' means is connected to the output such that the fourth set of input conditions establishes a path to the positive supply, the path having an impedance which is intermediate that of the low impedance and the high impedance. Alternatively, 'pull-down down' means is connected to the output such that the fourth set of input conditions establishes an intermediate impedance path to the negative supply.

Four-state I/O control circuit

The disclosed microprocessor time-shares an adder with a data memory, an accumulator, an I/O register, and an edge detector. This time-sharing is synchronized by a timing generator that produces interleaved first and second clocked pulses. Instructions are fetched from an instruction memory during the first clock pulses and are performed during the second clock pulses. To perform these instructions, the contents of the data memory and the accumulator are passed through the adder and fed back to the accumulator. In addition, during the first clock pulses, the contents of the I/O register and the output of the edge detector are passed through the adder and fed back to the I/O register. This allows the I/O register to be used as a counter while simultaneously allowing the structure of the I/O register to be greatly simplified.

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Sunnyvale, CA, United States of America

Ralph W Haines