Intel Corporation

Ralph Thomas Troeger

Rishabh Mehandru

Szuya S Liao

Jeffrey S Leib

Pratik A Patel

Daniel B Bergstrom

Gilbert W Dewey

Anand S Murthy

Leonard P Guler

Christopher J Jezewski

Nazila Haratipour

Nadia M Rahhal-Orabi

Michael Harper

I-Cheng Tung

Shakuntala Sundararajan

Kevin Cook

Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

Contact architecture for capacitance reduction and satisfactory contact resistance

Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of forming CMOS devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first metal over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, a second metal over the second source region and the second drain region, and the first metal over the second metal.

Dual contact process with stacked metal layers

Techniques and methods related to forming a wrap-around contact on a semiconductor device, and apparatus, system, and mobile platform incorporating such semiconductor devices.

Method of forming a wrap-around contact on a semiconductor device

Techniques and structures for protecting etched features during etch mask removal. In embodiments, a mask is patterned and a substrate layer etched to transfer the pattern. Subsequent to etching the substrate layer, features patterned into the substrate are covered with a sacrificial material backfilling the etch mask. At least a top portion of the mask is removed with the substrate features protected by the sacrificial material. The sacrificial material and any remaining portion of the mask are then removed. In further embodiments, a gate contact opening etched into a substrate layer is protected with a sacrificial material having the same composition as a first material layer of a multi-layered etch mask. A second material layer of the etch mask having a similar composition as the substrate layer is removed before subsequently removing the sacrificial material concurrently with the first mask material layer.

Sacrificial material for stripping masking layers

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Portland, OR, United States of America

Ralph Thomas Troeger