Delphi Technologies, Inc.

Uchicago Argonne, LLC

Delphi Technologies IP Limited

Ralph S Taylor

Erich William Gerbsch

Manuel Ray Fairchild

Michael A Jeter

John D Myers

Uthamalingam Balachandran

Carl William Berlin

Beihai Ma

William J Baney

Jeffrey J Ronning

Celine Wk Wong

Thomas Alan Degenkolb

David W Ihms

Tae H Lee

M Ray Fairchild

Steven Edward Staller

Roger A Mock

Andrew R Hayes

Celine W K Wong

Loren H Rasmussen

Uthamalingam Balachjandran

Erich W Gerbsch

A ceramic-wound-capacitor includes a first-electrically-conductive-layer, a dielectric-layer, a second-electrically-conductive-layer, and a protective-coating. The dielectric-layer is formed of lead-lanthanum-zirconium-titanate (PLZT). The protective-coating has a thickness of less than ten micrometers (10 &#x3bc;m) and provides electrical isolation between the first-electrically-conductive-layer and the second-electrically-conductive-layer of the ceramic-wound-capacitor. A method for fabricating the ceramic-wound-capacitor includes the steps of feeding a carrier-strip, depositing a sacrificial layer, depositing a first-electrically-conductive-layer, depositing a dielectric-layer, and depositing a second-electrically-conductive-layer to form an arrangement coupled to the carrier-strip by the sacrificial-layer, separating the arrangement from the carrier-strip and sacrificial-layer, creating an exposed-surface of the first-electrically-conductive-layer, applying a protective-coating to the exposed-surface of the first-electrically-conductive-layer, winding the arrangement with the protective-coating to form a ceramic-wound-capacitor, where the protective-coating is in direct contact with the first-electrically-conductive-layer and the second-electrically-conductive-layer of the ceramic-wound-capacitor.

Ceramic-wound-capacitor with lead lanthanum zirconium titanate dielectric

A ceramic-capacitor includes a first electrically-conductive-layer, a second electrically-conductive-layer arranged proximate to the first electrically-conductive-layer, and a dielectric-layer interposed between the first electrically-conductive-layer and the second electrically-conductive-layer. The dielectric-layer is formed of a lead-lanthanum-zirconium-titanate material (PLZT), wherein the PLZT is characterized by a dielectric-constant greater than 125, when measured at 25 degrees Celsius and zero Volts bias, and an excitation frequency of ten-thousand Hertz (10 kHz). A method for increasing a dielectric constant of the lead-lanthanum-zirconium-titanate material (PLZT) includes the steps of depositing PLZT to form a dielectric-layer of a ceramic-capacitor, and heating the ceramic-capacitor to a temperature not greater than 300&#xb0; C.

PLZT capacitor and method to increase the dielectric constant

A lead-lanthanum-zirconium-titanate (PLZT) capacitor on a substrate formed of glass. The first metallization layer is deposited on a top side of the substrate to form a first electrode. The dielectric layer of PLZT is deposited over the first metallization layer. The second metallization layer deposited over the dielectric layer to form a second electrode. The glass substrate is advantageous as glass is compatible with an annealing process used to form the capacitor.

PLZT capacitor on glass substrate

A ceramic short circuit resistant capacitor that is bendable and/or shapeable to provide a multiple layer capacitor that is extremely compact and amenable to desirable geometries. The capacitor that exhibits a benign failure mode in which a multitude of discrete failure events result in a gradual loss of capacitance. Each event is a localized event in which localized heating causes an adjacent portion of one or both of the electrodes to vaporize, physically cleaning away electrode material from the failure site. A first metal electrode, a second metal electrode, and a ceramic dielectric layer between the electrodes are thin enough to be formed in a serpentine-arrangement with gaps between the first electrode and the second electrode that allow venting of vaporized electrode material in the event of a benign failure.

Shapeable short circuit resistant capacitor

An electronic device assembly that includes a die and a substrate, and optionally a lead frame and a heat spreader. The die is characterized as an electronic device in die form, and has a polished die region. The substrate has a polished substrate region in direct contact with the polished die region. The polished die region and the polished substrate region have surface finishes effective to attach the die to the substrate by way of an atomic bond. The lead-frame has a polished lead-frame region, and the heat spreader has a polished heat spreader region. These polished regions may also be attached to the polished die region or the polished substrate region by way of an atomic bond.

Atomic level bonding for electronics packaging

A method that employs a novel combination of conventional fabrication techniques provides a ceramic short-resistant capacitor that is bendable and/or shapeable to provide a multiple layer capacitor that is extremely compact and amenable to desirable geometries. The method allows thinner and more flexible ceramic capacitors to be made. The method includes forming a first thin metal layer on a substrate; depositing a thin, ceramic dielectric layer over the metal layer; depositing a second thin metal layer over the dielectric layer to form a capacitor exhibiting a benign failure mode; and separating the capacitor from the substrate. The method may also include bending the resulting capacitor into a serpentine arrangement with gaps between the layers that allow venting of evaporated electrode material in the event of a benign failure.

Method of manufacturing a shapeable short-resistant capacitor

A capacitor exhibiting a benign failure mode has a first electrode layer, a first ceramic dielectric layer deposited on a surface of the first electrode, and a second electrode layer disposed on the ceramic dielectric layer, wherein selected areas of the ceramic dielectric layer have additional dielectric material of sufficient thickness to exhibit a higher dielectric breakdown voltage than the remaining majority of the dielectric layer. The added thickness of the dielectric layer in selected areas allows lead connections to be made at the selected areas of greater dielectric thickness while substantially eliminating a risk of dielectric breakdown and failure at the lead connections, whereby the benign failure mode is preserved.

Contact method to allow benign failure in ceramic capacitor having self-clearing feature

An electronics assembly is provided having a carrier that provides a controlled height variability between electronics packages and a heat sink device. The electronics assembly includes a substrate and electronics packages connected to the substrate. The assembly also includes a heat sink device positioned in thermal communication with a first side of the electronics packages. The assembly further includes a carrier disposed between the substrate and the heat sink device. The carrier has a resilient wall that biases the electronics packages towards the heat sink device such that a controlled bond line is provided between the first side of the electronics packages and the heat sink device.

Electronics assembly and electronics package carrier therefor

An electronics assembly is provided having a substrate and at least one electronics package supported on the substrate. The electronics package also has electrical circuitry and first and second side surfaces. The assembly further includes a first heat sink device positioned in thermal communication with the first side surface of the electronics package, and a second heat sink device positioned in thermal communication with the second side surface of the electronics package.

Electronics assembly having multiple side cooling and method

An electrically isolated and thermally conductive double-sided pre-packaged IC component, stamped lead members, drain pads, source pads, gate runner, and a MOSFET, IGBT, etc. are positioned between a pair of ceramic substrate members. Layers of solderable copper material are directly bonded to the inner and outer surfaces of the substrate members.

Electrically isolated and thermally conductive double-sided pre-packaged component

A power electronics module includes a heat sink and an electronic package having a first layer in direct thermal communication with the heat sink. At least one electronic component is disposed between the first layer and a second layer. A thermally conductive element is in direct thermal communication with the second layer and carries heat from a first portion of the second layer to a second portion of the second layer such that the heat is transferred from the second portion of the second layer to the heat sink through the first layer.

High power electronic package with enhanced cooling characteristics

An electrically isolated and thermally conductive double-sided pre-packaged IC component, stamped lead members, drain pads, source pads, gate runner, and a MOSFET, IGBT, etc. are positioned between a pair of ceramic substrate members. Layers of solderable cooper material are directly bonded to the inner and outer surfaces of the substrate members.

An electronics assembly is provided, including a housing and at least one electronic power device positioned within. A heat sink device is positioned within the housing and is in thermal communication with the electronic power device . The heat sink device includes a fluid vessel , a fluid input port , a fluid output port , and at least one fin insert brazed into the fluid vessel . The heat sink device is in fluid communication with an automotive radiator such that coolant flows from the automotive radiator through the fluid vessel thereby cooling the electronic power device

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Noblesville, IN, United States of America

Ralph S Taylor