Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Ralph Oberhuber

Jozef C Mitros

Franz Prexl

Wolfgang Steinhagen

Vadim Valerievich Ivanov

Timothy V Kalthoff

Mark Allan Shill

Ulrich Kaiser

Keith Brouse

Reiner Jumpertz

Kaiser Ulrich

Tsedeniya A Abraham

Prexl Franz

A non-linear correction current ICTAT(current complementary to the square of absolute temperature) is generated from a current IPTAT (current proportional to absolute temperature) and a current ICTAT (current complementary to absolute temperature), both modified in a circuit having a topology and components which capitalize on the logarithmic relationship between transistor collector current and base-emitter voltage. The resulting ICTATcurrent (current complementary to the square of absolute temperature) is injected into a node of a bandgap reference circuit to compensate for non-linear temperature effects on output voltage. A more general correction circuit generates both IPTATand ICTAT, and applies each to a respective multiplier which, in a preferred embodiment, is a current DAC configured as a multiplier. Control inputs CTLand CTLto respective multipliers set the amplitudes of the modified IPTATand ICTAToutput currents, which are then summed to generate the compensating current Icomp which is injected to the appropriate node in the bandgap reference circuit as described above. By adjusting the relative amplitudes of the IPTATand ICTATcurrents, a wide range of compensating current versus voltage curves is produced, allowing the optimization of a wide range of bandgap reference circuits. An optimal value for CTLis determined by holding CTLconstant, then measuring curvature at a plurality of CTLvalues. That CTLvalue closest to the interpolated value at which curvature is minimized is then used.

Method and circuit for curvature correction in bandgap references with asymmetric curvature

An apparatus is provided that comprises resistors, a first set of switches, and a second set of switches. The resistors are arranged in an array having columns and rows, where the number of resistors is an integer multiple of the number of columns or rows. The resistors are coupled together in a skip-K pattern. Each switch from the first and second sets of switches is coupled to the resistor string, and the first and second sets of switches are each arranged in a sequence and are offset from one another by an offset value. The first and second sets of switches are arranged along the periphery of the array such that each switch from the first set of switches is located in proximity to and is associated with the same row or the same column as its corresponding switch in the sequence from the second set of switches.

Digital-to-analog converter with a shared resistor string

Circuits and methods to minimize nonlinearity errors in interpolating circuits are described herein. A disclosed example circuit comprises first and second voltage-current converter circuits, each including a first transistor and a second transistor, each having a first electrode configured to receive a signal generated by a corresponding current source, a first current source providing a signal to the first voltage-converter circuit and comprising a first error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a first current through the first current source to operate the first voltage-converter circuit in a nominal linear operating mode, and a second current source providing a signal to the second voltage-converter circuit and comprising a second error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a second current through the second current source to operate the second voltage-converter circuit in the nominal linear operating mode.

Circuits and methods to minimize nonlinearity errors in interpolating circuits

An apparatus for compensating temperature changes in a temperature associated with a compensated device includes: (a) An input circuit having a first input locus for receiving a temperature-indicating signal and a second input locus for receiving a sign-indicating signal. The temperature-indicating signal indicates magnitude of the temperature. The sign-indicating signal indicates a first sign when a control signal is greater than a predetermined value and indicates a second sign when the control signal is less than the predetermined value. (b) A signal processing circuit coupled with the input circuit and with the host device for presenting a substantially a zero value temperature-compensating signal when the ambient temperature is at a predetermined level, and for presenting the temperature-compensating signal substantially opposite in polarity with substantially equal magnitude as the temperature-indicating signal received at the first input locus when the ambient temperature is not at the predetermined level.

Apparatus and method for compensating change in a temperature associated with a host device

An apparatus for adjusting a first signal with respect to a second signal includes: (a) A first converter receiving the first signal and employing n first converting elements for digitally converting the first signal to at least one first signal element. (b) A second converter coupled with an output, receiving the second signal and employing n second converting elements for digitally converting the second signal to a second representative signal presented at the output. (c) An adjusting element coupled with each of selected of the first converting elements. Each adjusting element is coupled with the output and cooperates with the connected selected element to present a corrected signal element to the output. The output presents an aggregate output signal including contributions from the second representative signal and each corrected signal element. Adjusting is effected by altering at least one corrected first signal element presented to the output.

Circuit for generating a temperature dependent current with high accuracy

A multi-stage circuit has a first stage powered by the output voltage of a next stage. A current source within the first stage provides a tail current for a differential amplifier within the first stage. When the first stage has an operating voltage high enough for proper operation, this tail current is at a nominal level; if the voltage is too low for proper operation of the first stage, the tail current is below this nominal level. A comparator, which has one input coupled to a node within this current source, a second input coupled to a threshold voltage, and an output coupled to a control node within the next stage, provides an output indicative of whether or not the tail current is substantially at its nominal level. If tail current is too low, the comparator provides a forcing signal to the control node of the next stage which causes the output of the next stage to be at a substantially nominal level regardless of the voltage at its input, thus providing a suitably high voltage for the first stage to begin normal operation. When the tail current reaches its nominal level, the comparator output changes state to one which has little or no effect on the output voltage of the second stage, and normal operation of the overall circuit begins.

Startup circuit for subregulated amplifier

The invention relates to a single-poly EPROM comprising a source, a drain, a control gate, a floating gate and an additional gate. The control gate is positioned laterally of a channel between the source and the drain. The floating gate is positioned above the channel above the control gate. The additional gate is positioned above the floating gate, wherein the additional gate is electrically connected to the control gate.

Single-poly EPROM device and method of manufacturing

A class AB output stage includes first (M) and a second (M) output transistors having sources coupled to first (V) and second reference voltages, respectively, drains coupled to an output (), and gates coupled to first (A) and second (A) conductors, respectively. Portions of first (I) and a second (I) input currents are sourced via a first input conductor () and a second input conductor (), respectively, into and from sources of first (M) and second (M) transistors, respectively. Gates of the first (M) and second (M) transistors are coupled to the first and second conductors, respectively. First (V) and second (V) bias voltages are applied to gates of third (M) and fourth (M) transistors respectively, having sources coupled to the first and second input conductors, respectively, and drains coupled to the second conductor.

Class AB output stage and method for providing wide supply voltage range

A single poly EPROM comprises a floating gate (), a control gate (), a source () and a drain (). The control gate () is positioned laterally of a channel between the source () and the drain (). The floating gate () is positioned above the channel and above the control gate (). The single poly EPROM device further comprises an additional gate () above the floating gate () and a control. The control is connected to the additional gate () for controlling a voltage at the floating gate () in order to prevent the floating gate () from being unintentionally charged or discharged.

Single poly EPROM device with double control gates to prevent unintentionally charging/discharging

Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer () and a first gate layer () and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (). A second capacitor structure comprising a second dielectric layer () and a second gate layer () is formed overlying the first gate structure. A source region () of a second conductivity type formed in the semiconductor substrate () proximate the first lateral side of the gate and a drain extension region/well () lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region () of the second conductivity type formed within the drain extension region (). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage. Other systems and methods are disclosed.

Drain extended MOS transistors with multiple capacitors and methods of fabrication

A transponder () comprising an antenna (), a demodulator () and a signal processing circuit () which converts a modulated signal received via the antenna () into a signal suitable for processing in the demodulator (). The signal processing circuit () comprises an amplifier () with a predefined amplification factor and a closed loop control circuit () serving to maintain the voltage swing of the processed signal applied at the input of the demodulator () substantially constant. In a preferred embodiment the closed loop control circuit comprises a capacitor which is continually discharged and differingly charged as a function of the strength of the output signal of the amplifier of the signal processing circuit, the voltage resulting across the capacitor controlling a controllable resistor connected in parallel to the input of the signal processing circuit and forming with a coupling capacitor a voltage divider.

Low power regulated amplifier for a transponder

A comparator with hysteresis which achieves fast switching despite a low current consumption. The comparator comprises a first transistor (M) and a second transistor (M) whose gates form the inputs of the comparator. The main current paths of both transistors are connected to each other at one end, with a third transistor (M) and a fourth transistor (M) being provided. The gate of the third transistor is connected to the gate of the first transistor and its main current path is circuited between the one end of the main current paths of the first and second transistor and is connected via the main current path of the fourth transistor to the other end of the main current path of the second transistor. The gate of the fourth transistor is connected to the output signal or inverted output signal of the comparator. The comparator in accordance with the invention may be put to use e.g. in an ASK demodulator such as those used in RFID transponders.

Comparator with hysteresis

A voltage follower comprising a first field-effect transistor (MN) whose gate forms the input of the voltage follower. Further provided is a second field-effect transistor (MN) whose drain connected to the gate forms the output of the voltage follower. The sources of the two field-effect transistors (MN, MN) are connected to each other and to the drain of a third field-effect transistor (MN) serving as current source and to the gate of which a predefined bias voltage is applied. The invention employs in addition a fourth field-effect transistor (MN) whose source-drain path is circuited between the output of the voltage follower and the drain of the third field-effect transistor (MN) and whose gate is connected to the gate of the third field-effect transistor (MN). As compared to prior art voltage followers the voltage follower in accordance with the invention comprises a wider voltage range in which it can be put to use. This can be made use of e.g. in amplitude shift-keyed (ASK) demodulators incorporating the voltage follower in accordance with the invention and which need to be operated with particularly small supply voltages.

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Kumhausen, Germany

Ralph Oberhuber