Smsc Holdings Sarl

Enq Semiconductor Inc.

Microchip Technology Inc.

Kleer Semiconductor Corporation

Synopsys, Inc.

Eno Semiconductor Inc.

Ralph Mason

Christopher Andrew Devries

Renyuan Li

Justin L Fortier

Chengbin Fan

Anita J Netherton

Andrew Burns

Dirk Pfaff

Robert Abbott

Ronald Douglas Beards

Jean-Paul Rene Decruyenaere

Chris Passier

Jean-Paul DeCruyenaere

William Kung

Christopher Falkingham

Brent Allen

Peter H R Popplewell

Chris DeVries

Anita Netherton

The present disclosure describes circuits (e.g., clock synthesizers) and methods for producing alternating signals. A clock synthesizer includes an oscillator, a voltage control circuit, and a frequency control circuit. The oscillator produces an output signal with a frequency. The voltage control circuit produces a control voltage for the oscillator based on the frequency of the output signal. The frequency control circuit produces a control signal for the oscillator based on (i) an input voltage to the frequency control circuit and (ii) the control voltage. The control signal causes the oscillator to adjust the frequency of the output signal such that the voltage control circuit adjusts the control voltage to be closer to the input voltage.

Clock synthesizer with dual control

In a wireless media network a source device provides entertainment content to a sink device over a radio frequency (RF) wireless channel. The source device can go into a receive only quiet enrolment mode until activated by a sink device transmitting enrolment trigger packets or having a signal strength above a certain threshold, thereby improving coexistence with other wireless devices. The source device changes from the quiet enrolment mode to an active enrolment mode when activated by the sink device.

Wireless quiet enrolment

Transmit power control functionality in wireless audio systems may be implemented by way of a Transmit Power Control (TPC) algorithm devised to control power for both source and sinks in a multi sink session, to reduce power consumption. Information may be passed back and forth between the source and sink devices to adjust power based on the shared information. The TPC algorithm may allow power control on both ends of an RF link, and may have multiple sink devices communicating with a source device. Furthermore, the multiple sink devices and the source device may each be operating at different power levels, and adjust their respective power levels as instructed by the TPC algorithm. Power control is therefore implemented on both ends of the link, where multiple sources and sinks may all operate at different power levels, and all individually adjust their respective power levels.

Transmit power control algorithms for sources and sinks in a multi-link session

A wireless audio device may realize power savings when processing multi-channel data, e.g. 2-channel stereo audio data, by splitting the multi-channel block data into separate data blocks for each channel, e.g. Left-channel data block and Right-channel data block, and processing each separate data block independently in the source device to generate respective data packets targeting corresponding sink devices, e.g. a Left earphone and a Right earphone. The source device may then transmit each data packet to a different corresponding sink device, e.g. a Left-channel packet to a Left earphone and a Right-channel packet to a Right earphone. The data packets may also include header information indicative of whether a next packet is intended for a given sink device, enabling sink devices to enter sleep mode when the header information indicates that a next packet is not intended for the given sink device, to save power.

Reducing power consumption in sink devices by having sinks receive only left audio channel or right audio channel

An audio amplifier system may include an audio CODEC/output (AOP) path featuring analog class-D amplifiers, and using Natural Sampling Pulse Width Modulation (PWM) to convert an analog input into a series of Rail-to-Rail pulses. The audio signal may be encoded in the average value of the PWM pulse train and may be recovered from the PWM signal by analog low pass filtering. The Class-D amplifiers may be designed with a negative feedback loop/network to compare the output signal with the input signal and suppress non-idealities introduced by the Class-D switching stage. Furthermore, operation of the AOP may be designed according to a separate signal transfer function and a separate noise transfer function, and 2order noise shaping may be performed at low power, with an optimized filter included in the feedback loop to achieve the best noise reduction at low power. Operation of the amplifier feedback network may be similar to that of a continuous time, low-pass delta-sigma modulator, but with a PWM loop wrapped around the class-D power amplifier.

Low-power class D amplifier using multistate analog feedback loops

Various embodiments of a radio-frequency (RF) transmitter receiver circuit that utilizes an injection locked oscillator may allow for the introduction of a DC offset to correct the RF signal. The DC offset may be adjusted to eliminate (or minimize) even order harmonics to correct for RF effects. The DC offset correction may be performed around the injection locked oscillator to target even order terms.

Reducing spurs in injection-locked oscillators

A wireless communications system and channel-switching method are disclosed herein. A source device and multiple sink devices independently maintain respective counters which track data packet errors. Each device independently switches channels only after its counter reaches a channel-switching threshold. The new channel switched-to is either determined by an indexed ordering of the available channels or by reference to a global clock maintained by each of the devices. Accordingly, all devices quickly arrive at a common channel. The system switches channels only when necessary and resolves quickly to a mutually acceptable channel. Therefore, unnecessary channel switching is minimized and data throughput is optimized.

Wireless communications systems and channel-switching method

Systems and methods related to digital frequency locked looping to synchronize frequencies between the local signal from a local oscillator and a reference clock signal from a remote oscillator. A reference counter increments its count for every pulse in the reference clock signal. The value in the reference counter is compared to a configurable reference value. Whenever a match between the reference counter value and the reference value occurs, a hit signal is generated and the reference counter value is reinitialized. Concurrent with the above, a feedback counter increments for every pulse from the local signal. When the hit signal is generated, the value in the feedback counter is compared to a configurable feedback value (by subtraction) to generate a difference value. The difference value is then converted to a frequency adjust signal for use in either increasing or decreasing the frequency of the local oscillator. The hit signal also reinitializes the feedback counter.

Frequency synchronization

The invention relates to the field of wireless communications and more specifically to an high quality, low power wireless audio system. More specifically, the invention comprises an audio source for receiving audio signals (e.g. music) and audio status information (e.g. song title) from a first external device (e.g. an MP3 player) and transmitting the audio signals and the audio status information over a wireless connection; and at least one audio sink for receiving the audio signals and said audio status information from the audio source and communicating the audio signals and the audio status information to a second external device (e.g. headphones), wherein a specified one of the at least one audio sink receives audio control information (e.g. pause) from the second external device and transmits said audio control information to said audio source via said wireless connection. Among other features, the wireless audio system of the present invention incorporates dynamic channel selection as well as dynamic adjustment of the transmission interval to ensure enhanced audio quality using the lowest possible power.

High quality, low power, wireless audio system

An improved receiver architecture and method for a wireless transceiver (e.g. for a headphone) is provided whereby the receiver, advantageously, enables the use of only one synthesizer circuit for both the RF-to-IF and IF-to-base band conversion processes which, in turn, provides for lower power consumption. The receiver includes an injection locked local receiver oscillator (Rx LO) which is used for the first mixing stage (i.e. the RF-to-IF conversion). The Rx LOis thereby able to use a high-level harmonic of a relatively low reference frequency signal produced by that synthesizer (e.g. a fractional-N phase locked loop circuit (PLL)). The receiver further includes a tunable Q-enhanced IF filterand complex sub-sampling and mixing down-conversion circuitry for the second conversion stage (i.e. IF-to-baseband conversion). The sampling frequency used for the second conversion stage is a harmonic of the reference frequency derived from the synthesizer (PLL). For example, transceiver channels may be designed on the basis that the RF frequency fis assigned a value of (n&#xb1;&#xbc;)&#xb7;f, where the frequency fof the PLL may be chosen to be twice the sub-sampling frequency fand the frequency fof the Rx LO may be nine times the frequency f.

RF-to-baseband receiver architecture

A Method for filter tuning using direct digital sub-sampling is provided. The tuning is accomplished in the digital domain by determining the filter characteristics from the shape of the transfer function. The input signal () is passed through the filter () and is then sub-sampled by and Analog-to-digital Converter (ADC) (). The sub-sampled signal () is then processed in the digital domain using a digital circuit () that is used to determine the center frequency (Fc) and Quality factor (Q) and/or other important filter parameters. The Fc, Q and/or other important filter parameters are then adjusted by generating digital control signals () that can be converted to analog signals () using Digital-to-analog Converters (DACs) ().

Directly tuned filter and method of directly tuning a filter

The invention relates to the field of electronics and more particularly to the tuning and injection locking of voltage controlled oscillators (VCOs). An improved injection locking circuit is provided which allows the VCO to injection lock with a smaller reference signal and therefore a smaller locking bandwidth (LBW). In order to allow the VCO to injection lock with a lower power reference signal, this invention includes a pre-tuning algorithm to place the VCO frequency such that the desired frequency is in the LBW. Tuning of the VCO is achieved using direct digital tuning that does not require an input reference. Injection locking is performed using a low frequency clock harmonic as the reference signal. More specifically, tuning is accomplished by sub-sampling and digitizing the output signal of the VCO, determining the center frequency, and adjusting the VCO control voltage.

Injection locking using direct digital tuning

A power down system and method for an integrated circuit that enables a power down mode to be maintained for a predetermined time is described herein. The power down system comprises an oscillator, a low power oscillator and an oscillator control circuit controlling both the oscillator and the low power oscillator. The oscillator control circuit including at least one real time counter. The oscillator control circuit being so configured that the oscillator is energized when said oscillator control circuit is in a normal mode and that, when a power down signal is received: a) the oscillator control circuit measures an oscillation frequency of the low power oscillator, b) the oscillator control circuit uses the measured oscillation frequency of the low power oscillator to set the real time counter so as to maintain the power down mode for the predetermined time, c) the oscillator control circuit turns off the oscillator and uses the low power oscillator for the duration of the power down.

Power down system and method for integrated circuits

The invention relates to electronic &ldquo;sample and hold&rdquo; circuits and, in particular, to such circuits which may implemented in integrated form. A method and circuit are provided for improving isolation during the hold mode of operation of a sampling circuit. An input differential signal is provided to parallel circuit paths (viz. a primary sampling path and an isolation path) which are identical (electronically equivalent) and, therefore, provide the same impedance leading to hold capacitor(s). The circuit paths are configured, relative to the differential inputs, so that any feed through (leakage) of the differential input signal is subtracted (cancelled) during the hold mode.

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Ottawa, Canada

Ralph Mason