International Business Machines Corporation

Ralph M Begun

Patrick M Bland

Mark Edward Dean

Christopher M Herring

Justin Potok Bandholz

Richard Bealkowski

Andrew S Heinzmann

William R Greer

Fernando Aramis Lopez

Michael Robert Turner

Michael Sven Miller

Raymond Mathew Clemo

Vinod Kamath

Mark William Kellogg

Michael DeCesaris

Louis Bennie Capps, Jr

Karl Klaus Dittus

Marc Raymond Faucher

Randolph Scot Kolvick

Adam Lee Soderlund

Steven L Vanderlinden

Philip E Milling

Warren E Price

Whitcomb Randolph Scott, Iii

Brian Gormley

Gerald L Frank

Paul W Browne

Methods, apparatuses, and computer program products for dynamically reconfiguring a primary processor identity within a multi-processor socket server are provided. Embodiments include detecting, by the service processor, a processor socket reconfiguration event corresponding to a first processor socket; disabling, by the service processor, the first processor socket of the server in response to detecting the processor socket reconfiguration event; and reassigning, by the service processor, the primary processor identity to a second processor socket of the server.

Dynamically reconfiguring a primary processor identity within a multi-processor socket server

This invention enables authenticated communications (transactions) to take place on a standard IC bus without requiring modification of existing IC devices. Read and write transactions occurring on the bus are authenticated using an Authentication Agent and a shared secret key. In addition to allowing verification of the legitimacy of the transactions, the authentication of the IC transactions enhances the reliability and serviceability of the bus and devices on the bus by allowing the Baseboard Management Controller (BMC) to quickly determine and pinpoint errors.

[object Object]

A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is for securing of leased resources on a computer. The design structure includes a computer for securing resources may comprise at least one processor, a plurality of resources, wherein each resource is associated with configuration data and a programmable logic device connected to each of the plurality of resources. The programmable logic device may be configured for determining whether a resource is leased, reading un-encoded configuration data from a resource, and sending the configuration data to a first unit, if the resource is not leased. The programmable logic device may further be configured for reading encoded configuration data from a resource, decoding the configuration data, sending the configuration data that was decoded to a first unit, and logging use of the resource by the first unit, if the resource is leased.

Structure for securing leased resources on a computer

In one embodiment, a single electrical power supply is used to interchangeably power either a single motherboard or dual motherboards. Switchable output power and individual sequencing may be provided to each motherboard using FETs, such that the power supply may respond to the sequencing of each motherboard as if it were dedicated to that motherboard. In a two motherboard system, power to the first motherboard is reduced by removing some output voltages from the first motherboard. Fault circuitry may also be provided so that a power related fault on one domain does not affect operation of the other motherboard.

System and method for interchangeably powering single or multiple motherboards

A system comprising a chassis that includes a plurality of modules and a fan assembly disposed in a distal end of the chassis for drawing air in parallel pathways through the plurality of modules. At least one of the modules is a compute module having a thermal sensor disposed to sense the temperature of air flowing across a processor mounted on a motherboard. The system further comprises a fan controller receiving output from the thermal sensor, wherein the fan controller operates the fan assembly to cool the plurality of modules and maintain the thermal sensor output within an operating temperature range. The fan controller controls the fan speed according to predetermined thermal profile settings associated with one of the compute modules received in the chassis. For example, the predetermined thermal profile settings may include a minimum fan speed, a maximum fan speed, and control loop feedback settings.

Plurality of configurable independent compute nodes sharing a fan assembly

Embodiments of the invention provide a novel and non-obvious method, system and computer program product for securing of leased resources on a computer. In one embodiment of the invention, a computer for securing resources may comprise at least one processor, a plurality of resources, wherein each resource is associated with configuration data and a programmable logic device connected to each of the plurality of resources. The programmable logic device may be configured for determining whether a resource is leased, reading un-encoded configuration data from a resource, and sending the configuration data to a first unit, if the resource is not leased. The programmable logic device may further be configured for reading encoded configuration data from a resource, decoding the configuration data, sending the configuration data that was decoded to a first unit, and logging use of the resource by the first unit, if the resource is leased.

Securing leased resources on a computer

In a multi-node SMP system, at least one processor per node is enabled to execute the SMM task for the hardware resources that are local to that node. Additionally, each node is allocated its own local SMM code copy in its own SMM memory segment, to allow for improved access and a further reduction in internode traffic. In a preferred embodiment, only a signle processor per node is enabled to execute the SMM tasks, and specific SMM memory locations within the SMM memory segments are allocated and used to report status and results from each node. A root node SMM processor monitors the SMM status entries of the other nodes for completion. To further reduce run-time internode traffic, a per-node resource map is created to identify memory and I/O resources that are specific to a particular node. This per-node resource map is then stored locally within the SMM space on each node, respectively.

System management architecture for multi-node computer system

A personal computer system is provided which includes a CPU, with the CPU being operable by a BIOS including initialization or booting instructions. The system includes a local bus and a peripheral bus. A bus interface chip, including a memory controller/peripheral bus host bridge (MC/PBHB) interconnects the local bus and the peripheral bus, and includes a latch which includes as its input clock cycles generated by the CPU. The initialization instructions of the BIOS are contained in a non-volatile ROM module located to write onto either the local bus or the peripheral bus. The MC/PBHB unit is able to decode and handle ROM cycles and is configured to either pass or not pass ROM read cycles depending upon certain control states that identify whether the ROM is located on the local bus or the peripheral bus. Logic is provided to detect during the first ROM CPU cycle whether the ROM is on the peripheral bus or on the local bus, and the MC/PBHB will then either pass the signal to the peripheral bus if that is where the ROM is located, or will not pass it--in which case the local bus controller will take over and read the ROM which must be located on the local bus since it is not located on the peripheral bus.

Computer system for detecting and accessing BIOS ROM on the local or

A programmable firmware store for a personal computer system includes a plurality of nonvolatile alterable electronic memories connected in a mutually paralleled circuit arrangement. The memories are connected to a controller that controls the memories to read firmware from and write firmware into the electronic memories, and to write-protect at least one of the memories. Any memory can be write-protected as initially selected by a user or technician of the system. The initial selection can be changed easily to write-protect another of the memories. The firmware in one memory includes code for checking the validity of firmware stored in another memory, and for selecting one or the other of the memories dependent upon a version code of the firmware. The controller also includes an update code for updating the firmware in a selected memory.

Method and apparatus for providing updated firmware in a data processing

An automated programmable firmware store for a personal computer system includes a plurality of nonvolatile alterable electronic memories connected in a mutually paralleled circuit arrangement. The memories are connected to a means for automatically controlling the memories to read firmware from and write firmware into the electronic memories, and to write-protect at least one of the memories. Any memory can be write-protected as initially selected by the automatic control means. The initial selection can be changed easily to write-protect another of the memories. The firmware in one memory includes code for checking the validity of firmware stored in another memory, and for selecting one or the other of the memories dependent upon a version code of the firmware. The control means also includes an update code for updating the firmware in a selected memory. The automated store further includes means for allowing the computer system to recover automatically from invalid firmware stored in one of the memories.

Automated programmable fireware store for a personal computer system

Computer system for detecting and accessing BIOS ROM on local bus

Computer system and method of operation thereof wherein a BIOS ROM can

A write compression buffer is connected to a CPU bus and to a memory controller to provide write cycle compression in which plural partial write requests to the same memory address are compressed into a single memory write cycle. The buffer has a plurality of buffering level.

System for combining data from multiple CPU write requests via buffers

The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

Microcomputer system employing address offset mechanism to increase the

A multiprocessor computer includes a planar board and a processor card mounted on the planar board. An interrupt controller is mounted on the planar board and has a plurality of interrupt input lines for receiving interrupt requests from a plurality of interrupting devices. The interrupt controller also has an output line that transmits an interrupt to the processor card. The processor card includes an interrupt director having a plurality of interrupt request lines respectively connected to interrupt request pins of the different processors. The director is also connected to the output line coming from the interrupt controller. In response to receiving an interrupt request from the interrupt controller, the director performs an interrupt acknowledge cycle and transmits an interrupt request, on only one of the interrupt request lines, to a specific processor predetermined by the director. The specific processor then reads an interrupt vector from the director. The interrupt vector uniquely identifies the interrupt level and is used by the processor to execute an interrupt handler for that specific interrupt level.

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Boca Raton, FL, United States of America

Ralph M Begun