International Business Machines Corporation

Sk Hynix Memory Solutions Inc.

Ralph L Gee

Robert W Anderson

Martin Aureliano Hassner

Arvind M Patel

Paul Wingshing Chung

Paik Saber

Luke C Lang

Jasper A Indelicato

Trung L Nguyen

Processing a received signal includes receiving a code word that is different from an expected code word, determining, at least in part using a logic circuit, whether the difference between the received code word and the expected code word is acceptable based at least in part on one or more bit differences, and in the event it is determined that the difference is unacceptable, providing an indication of an error.

Programmable gray code bit change generator

In a digital multiplier for multiplying two multi-bit binary operands to produce a binary result by means of a lookup table containing all possible products of said operands, reduction of the total amount of memory required to store the table is obtained by segmenting one operand into a plurality of non-overlapping bit groups and constructing lookup tables for the bit groups, in which each lookup table contains products of its associated bit group and the other, non-partitioned operand. Multiplication is accomplished by generating partial products from the lookup tables, shifting the partial products to account for the relative significance of their associated bit groups, and adding the partial products to provide the resultant product.

Table lookup multiplier with digital filter

A bit-serial division method for computing the value v/u, where v and u are each n-bit vectors that are elements in a finite Galois field GF(2.sup.n) consisting of 2.sup.n elements. The n-bit components of each element in the field are coordinates of the element in a canonical basis of the field. Vector u is converted from canonical basis to a dual basis. Vector u in dual basis also comprises n bits in the finite field ordered according to an index i that takes on values from 0 to (n-1). All bits n of the converted vector u are loaded into a shift register in parallel, then converted from dual basis back to canonical basis to produce a single bit output w.sub.0 from a lookup table which generates bitwise the inverse of the n-bit vector u. The bits in the shift register are shifted (n-1) times to generate successive additional single bit outputs w.sub.i with said lookup table. Then each bit w.sub.i is multiplied by the vector v and a corresponding element c.sub.i in dual basis to generate a cumulative sum of these products that provides, upon completion of the (n-1) shifts, the bit-serial division result v/u.

Bit-serial division method and apparatus

A method and means for setting the free-running frequency of a voltage controlled oscillator (VCO) without requiring laser trimming or the like is described. The VCO forms part of an interconnected phase-locked loop (PLL) and frequency-locked loop (FLL). At system power on, the PLL is automatically disabled and a digital-to-analog (DAC) in the PLL is set to a value corresponding substantially to the center of a preselected lock range. The FLL, which includes a second DAC, then operates to generate a bias voltage for incrementing or decrementing the VCO output frequency until the VCO pulse count stored in a register equals an expected count; whereupon the VCO will be set at its free-running frequency. When the PLL is enabled, a phase error generator generates a digital phase error signal from the input data. A digital integrator converts the phase error signal to a digital frequency error signal. These error signals are added and the result is supplied to the DAC in the PLL for providing an analog output indicative of PLL frequency error. The outputs from both DACs are summed and the resultant current is converted to a bias voltage to adjust the VCO frequency as necessary for normally maintaining it within said lock range. If the VCO frequency deviates from said range, the frequency error signal to the PLL DAC is zeroed, and the frequency error signal is supplied to the FLL DAC. The phase error signal from the PLL DAC and the signal from the FLL DAC as modified by the frequency error signal are summed, and the resultant current in converted to a bias voltage to adjust the VCO frequency to within said lock range.

Setting and dynamically adjusting VCO free-running frequency at system

A method and apparatus is disclosed that is selectively conditionable, during read processing, to operate in normal or diagnostic on-the-fly mode or in normal or diagnostic deferred mode to correct errors in encoded uncorrected data in a disk storage device. During deferred mode operation, hardware in the disk storage device receives uncorrected data in real time and generates syndrome bytes which are decoded at the device into error pattern and error location information that is transmitted to a storage director. Circuitry is provided for retaining, if desired, error pattern and location information to facilitate identification of surface defects in the storage disk whether read processing was done on-the-fly or in deferred mode.

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San Jose, CA, United States of America

Ralph L Gee