International Business Machines Corporation

Ralph James Williams

Daria Rose Dooling

Gary S Ditlow

David Erin Moran

Thomas Wood Wilkins

Stephen D Thomas

Jason D Hibbeler

Robert J Allen

Daniel Nelson Maynard

Sarah C Prue

Richard L Moore

Gustavo Enrique Tellez

William C Leipold

Edward Hugh Welbon

Kenneth T Settlemyer, Jr

Timothy G Dunham

Jacek G Smolinski

James R Robinson

Robert P Battaline

Cassondra L Crotty

A method and structure for determining a listing of host processors on a network to perform a parallel application, including determining a listing of all possible hosts on the network for performing the parallel application, determining for each of the possible hosts a current capacity and a current utilization, calculating for each of the possible hosts a difference between the current capacity and the current utilization, and selecting from the listing of all possible hosts a listing of hosts based on sorting the calculated differences.

Method and apparatus to manage multi-computer supply based on an economic model

An integrated circuit system and program product for predicting yield of a VLSI design. An integrated circuit system is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each different region is associated with a circuit type; a tallying system for calculating a plurality of tallies of critical area values based on circuit type; and a plurality of modeling subsystems for separately modeling each of the plurality of tallies based on circuit type.

Content based yield prediction of VLSI designs

Method and apparatus to manage multi-computer supply using a model based on an economic model of supply and cost of supply

A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.

Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data

A system, method and program product for predicting yield of a VLSI design. A method is provided including the steps of: identifying and grouping sub-circuits contained within an integrated circuit design by type; calculating critical area values for regions within the integrated circuit design; and applying different yield models to critical area values based on the types of the regions used to calculate the critical area values, wherein each yield model is dependent on a type.

A system and method for visualizing data. Data are provided either in the form of data values of a data array or in the form of a geometric representation. A data array may be, for example, a sparse matrix. A geometric representation, may be, for example, an integrated circuit layout coded in a geometric description language. Data provided in the form of data values are associated with geometric shapes placed on a grid. Information placed on the grid is then reported to a user. If data are provided in the form of a geometric representation, then data values are extracted from the geometric representation. A graphic representation is generated from the extracted data values. The graphic representation is exhibited to a user.

Method for visualizing data

Method and apparatus to manage multi-computer supply

A method, multi-computer media and apparatus that uses an economics model to manage the demand and the resource satisfying that demand for multi-computer memory. The present invention quantifies demand as a function of space, and computer resource as a function of time, so that a computational system can meet an application demand.

Method and apparatus to manage multi-computer demand

Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical blocks and repeats the process of identifying logical blocks for different hierarchical levels of the integrated circuit design until the number of logical blocks is within the range of the desired number of logical blocks. This serves as a guide to partition the chip as opposed to a grid-like partitioning.

Autonomic graphical partitioning

The present invention divides a large graphics file into smaller &ldquo;frames&rdquo; of graphics files. The division process is preferably load balanced amongst any number of processors. This allows many processors to be used in parallel to divide the large graphics file and to then process the smaller output frames. Additionally, the load balancing is performed in such a manner that only portions of the graphics file need be loaded by any one processor. This saves memory and computational requirements. Preferably, the graphics file is divided in a three-dimensional manner, such that any one processor will be assigned one three-dimensional block or volume of the graphics file. The three-dimensional partition of the graphics file will become one frame, and the one processor accesses the graphics file to copy its three-dimensional partition into the new output frame.

Partitioning and load balancing graphical shape data for parallel applications

A method is provided for designing an integrated circuit that includes receiving a graphical description of the integrated circuit, extracting shapes relating to a specific circuit function from the graphical description of the integrated circuit, and partitioning the extracted shapes into a plurality of segments. The method may form an electrical representation of the integrated circuit for each of the plurality of segments and solve a matrix equation (Gv&equals;i) for each of the plurality of segments based on the electrical representation.

Method to partition the physical design of an integrated circuit for electrical simulation

A method for manufacturing an integrated circuit having improved defect-limited yield. Each conductor on the integrated circuit is represented as an electrical element of a network, having branch voltages and currents. The width of the conductor is advantageously selected to have the minimum width necessary to produce signal levels that have sufficient noise margins. An integrated circuit conductive grid is thus realized having a reduced cross sectional area along a portion of various conductor element lengths, to reduce the risk that particles produced during manufacturing will result in bridging of adjacent conductor elements.

Method to improve integrated circuit defect limited yield

Disclosed is a system and method of providing performance analysis on integrated circuit devices and systems using an IEEE JTAG 1149.1 interface. An integrated circuit device is described that includes an execution control register for receiving a control code from an external device via the JTAG interface, a means for selecting and coupling to one or more specific logic circuits on the device, one or more counters for recording specific events occurring on the logic circuits, and a counter register for managing the counter data and outputting it via the JTAG interface.

Growing community of inventors

Essex Junction, VT, United States of America

Ralph James Williams