Other

Agilent Technologies, Inc.

Texas Instruments Corporation

Hewlett-packard Company

Ralph H Lanham

Hugh Pryor McAdams

James W Grace

Juergen T Rickes

John Y Fong

Daryl E Anderson

Neal C Jaarsma

David Victor Pietromonaco

An integrated circuit (IC) chip contains a small non-volatile 'ID' memory such as an FeRAM array that stores information associated with manufacturing, testing, and performance of the IC chip. The stored information can include but is not limited to a serial number, a wafer ID, a batch ID, a date code, chip history, test data, and performance information. The storing information on the chip eliminates any difficulty in matching the information with the IC chip and provides a flexible permanent record of any information the manufacturer may find useful. The ID memory thus permits tracking and identification of ICs to a degree that was not previously practical. Additionally, a self-test can compare prior test results stored in the ID memory to current self-test results to detect defects or to select operating parameters of the integrated circuit.

Permanent chip ID using FeRAM

A memory such as a FeRAM implements accelerated fatigue operations that simultaneously change the storage state of large numbers of memory cells and can be rapidly repeated. In one embodiment, the FeRAM includes multiple segments with plate lines in each segment being isolated from plate lines in other segments. A first fatigue operation uses standard read/write decoding for word lines but simultaneously activates all segments. A second fatigue operation activates all segments and all plate lines and exercises one row of memory cells in each plate line group. A third fatigue operation is similar to the second but cycles through rows in the plate line groups so that a number of repetitions of the third fatigue operation equally fatigue every FeRAM cell.

Accelerated fatigue testing

An apparatus and method for shortening the read operation (typically the longest operation) in a destructive read memory is disclosed. The rewrite step is separated from the read operation and delayed to the subsequent clock cycle. A FeRAM memory cell having two ports is needed so that consecutive operations do not conflict with each other. A read operation is initiated through a first port in a first clock cycle. In the subsequent clock cycle, the rewrite finishes through the first port. The next operation utilizes the second port, without conflicting with the rewrite process. By alternating ports used in each clock cycle, the rewrite step is hidden in the subsequent clock cycle to shorten the read operation. In an alternate method, all read operations are initiated through one port, while the second port is reserved exclusively for write operations and rewrites.

Method and apparatus for shortening read operations in destructive read memories

A method and circuit for measuring a charge distribution for readout from FeRAM cells is fast enough for an on-chip defect detection and parameter adjustment. A comparator-type sense amplifier and a reference voltage generator measure a bit line charge or voltage using one readout of charge from an FeRAM cell and comparisons of the resulting bit line voltage to a series of reference voltages. A series of result signals from the sense amplifier indicates when the bit line voltage is approximately equal to the reference voltage. The results signals can be output for analysis and/or used internally for defect detection or setting of operating parameters such as a reference used during read operations.

On-chip charge distribution measurement circuit

A method for testing a systolic array in which a plurality of sequential registers is each connected to the rest by an intervening logic component. Each register includes a plurality of memory elements. Each register can be enabled to act as a latch register whereby digital data is loaded into an output therefrom in parallel or as a shift register whereby digital data is shifted sequentially in each register from one memory element to the next adjacent memory element. A test vector consisting of a preselected string of digital data is shifted in parallel into each of the registers. The test vector in each register is loaded into the associated logic component which operates on the vector and stores the data in the next adjacent register. The resulting data is serially clocked from each register onto unique bus nodes and examined in parallel to determine whether or not the expected result was obtained.

Growing community of inventors

Cupertino, CA, United States of America

Ralph H Lanham