Motorola Corporation

Ralph E Snowden

Eugene H Gruender, Jr

Charles Christopher Hill

Hing Leung Yiu

Douglas R Kraft

Glen James Zoerner

Wendy Reed

Harold K Williamson

Wai-Kin Steven Kwan

On Ki Chu

Rajesh Mangal

James Holbrook

Robert D Whitley

Flow control in a distributed switch fabric () includes detecting at least one of a congestion condition () in a downstream transceiver port () and an oversubscribing condition () of a channel buffer (), where the downstream transceiver port () and the channel buffer () both correspond to a channel () of a traffic manager (). Packets begin accumulating in the channel buffer (). Per-flow flow control () operates to modify transmission of the packets over the channel () to the channel buffer () if the channel buffer () reaches a threshold value (). Link level flow control () operates transparently to the traffic manager () if the congestion condition () is detected and the channel buffer () fails to reach the threshold value ().

Method of flow control

When an external reset signal EXRST is asserted received by a reset unit (6), it is synchronised with an internal clock to produce an internal reset signal INRST, which is applied to a CPU (4) and other modules in the circuit to reset them. While the internal reset signal INRST is being applied to the CPU, the rate of a refresh signal being generated by a DRAM controller (7) for refreshing data in DRAM (3) is increased. Then, when the external reset signal EXRST is disabled, a delayed reset signal DLYRST is generated and applied to the DRAM controller (7) so that it is reset. The CPU, being already reset, can then quickly reconfigure the DRAM controller and re-enable it to resume refreshing the DRAM (4), thus maintaining the data in the DRAM.

Circuit and method for retaining data in DRAM in a portable electronic

Initialization data is received by a memory multiplexer (MEMMUX) and stored in a plurality of registers of the MEMMUX without reading data from memory. The storage of the initialization data in the MEMMUX registers may be sequential or simultaneous. The initialization data is then written to memory along with error detection and correction data as desired.

Demultiplexing initialization data to be transferred to memory through a

A burst error scrubbing system and method consecutively detects and corrects errors in all of memory, beginning with data stored at the first address of memory and continuing until data stored at the last address of memory is read, corrected and written back to memory. Burst error scrubbing is not performed during a refresh cycle but instead is programmable so that the burst scrubbing can be performed at a specific time interval.

System using a memory controller controlling an error correction means

A circuit comprising first, second and third latches selectively extends a cycle of a clock signal of a memory system in response to a control signal. A second clock signal having a frequency which is a predetermined multiple of the clock signal of the memory system is coupled to an input of the second and third latches. The first latch receives first and second control signals indicating the detection of parity errors in the memory system and suspends or delays the normal transition of the third latch which provides the memory system clock signal, thereby extending a cycle of the clock signal. The second latch resets the first latch which thereafter resets the third latch causing the clock signal to return to normal cycle operation.

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Austin, TX, United States of America

Ralph E Snowden