Analog Devices,inc.

Ralph David Moore, Jr

Jesse R Bankman

Peter Delos

Javier Alejandro Salcedo

Ahmed Mohamed Abdelatty Ali

Srivatsan Parthasarathy

Franklin Marshall Murden, Ii

Scott Gregory Bardsley

Ryan Lee Bunch

Rodney Dean Miller

Frank M Murden

Carroll Clifton Speir

Bryan Scott Puckett

Brad Porcher Jeffries

Michael Joseph Fernald

George F Diniz

John P Guido

Charles O'Roark

Herein disclosed are systems and circuitry for protecting against overdrive and electrostatic discharge. For example, protection circuitry may include field effect transistors to discharge overdrive outside of an operational voltage range of a circuit in some embodiments to prevent damage to the circuit. Further, the protection circuitry may utilize diode features inherent in the field effect transistors to protect against electrostatic discharge in some embodiments. The circuitry may be implemented in radio frequency sampling analog-to-digital converters and can provide for single-ended signal input and/or output for the analog-to-digital converters.

Electrostatic discharge and overdrive protection circuitry

Provided herein are apparatus and methods for a multi-stage signal-processing circuit. The signal-processing circuit can include multiple configurable stages that can be cascaded and configured to process an input signal. Control circuitry can be used to select an output of the configurable stages. Serial data can be recovered with good signal integrity using a signal monitor with the configurable stages by virtually placing the signal monitor on a buffered output node.

Adaptable receiver amplifier

Multiplying digital-to-analog converter (MDACs) are implemented in pipelined ADCs to generate an analog output being fed to a subsequent stage. A switched capacitor MDAC can be implemented by integrating a capacitor digital-to-analog converter (DAC) with charge pump gain circuitry. The capacitor DAC can implement the DAC functionality while the charge pump gain circuitry can implement subtraction and amplification. The resulting switched capacitor MDAC can leverage strengths of nanometer process technologies, i.e., very good switches and highly linear capacitors, to achieve practical pipelined ADCs. Moreover, the switched capacitor MDAC has many benefits over other approaches for implementing the MDAC.

Switched capacitor comparator

Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.

Track and hold circuits for high speed and interleaved ADCs

Switched capacitor multiplying digital-to-analog converter

A time-to-digital converter (TDC) detects a timing relationship between signals representing two temporal events. Several samples are acquired over a certain time period for each event, and the signals related to the different events are digitized or quantized either by separate TDCs or by a single TDC in a time-sequential manner. The quantized results are then processed, for example added to/subtracted from one another, and used to determine the phase or time difference between the two events. When information being quantized is quasi-static over time periods where the measurement is performed, the instantaneous or 'one shot' accuracy of a TDC need not be as good as or better than the desired time resolution. Digitally processing the signals and averaging the results moves an otherwise difficult analog quantizer problem to the digital domain where savings in power and chip area can be easily achieved without sacrificing accuracy.

Open loop oscillator time-to-digital conversion

In pipelined analog-to-digital converters (ADCs), a passive switched capacitor (PSWC) circuit can be used in a multiplying analog-to-digital converter (MDAC), which generates an analog output being fed to a subsequent stage. Complementary analog input signals are sampled respectively onto first and second capacitors, which are stacked to provide gain. The first capacitor is positioned between a first input switch and an output node of the PSWC circuit, and the second capacitor is positioned between the second input switch and a digital-to-analog converter (DAC) output. The topology advantageously isolates common modes of the complementary analog input signals, the DAC output, and the output of the PSWC circuit. As a result, the topology offers more degrees of freedom in the overall circuit design when stages having the MDAC are cascaded, resulting in pipelined ADCs with a more elegant design with lower noise and lower power consumption.

Passive switched capacitor circuit for sampling and amplification

An exemplary level shifter includes a clock level shifter configured to generate a level shifted clock signal from an input clock signal; and a switched capacitor logic controller coupled to the clock level shifter. The switched capacitor logic controller is configured to steer the level shifted clock signal based on a data signal and the input clock signal, providing a level shifted version of the data signal.

Level shifter

In an embodiment, a primary charge pump and replica charge pump may be coupled to matching control mechanisms and loads. In an embodiment, the replica charge pump may produce an error current originating from charge pump timing mismatches in a steady locked loop state. The error current produced by the replica charge pump may be measured by a difference amplifier to adjust at least one current source to compensate for the error current originating from the timing mismatches. To adjust the current sources, the amplifier may cause the current source to produce an equal but opposite current to cancel the effects of the error current, resulting in a constant output voltage.

High speed DLL offset cancellation

Activation systems and methods initiate High-Definition Multimedia Interface (HDMI) communication between an HDMI source and an HDMI sink through an HDMI receptacle of the source. These systems and methods are especially suited for use with mobile sources that generally operate from a battery that cannot provide the +5V signal which the HDMI protocol requires sources to place on the +5V pin of their HDMI receptacles. These systems and methods automatically detect the insertion of an HDMI cable into the source's HDMI receptacle and subsequently generate and apply the required +5V signal to the +5V pin of the source's HDMI receptacle to initiate HDMI communication. Because they are directed to use in mobile sources, the embodiments are configured to minimize current drain.

Activation systems and methods to initiate HDMI communication with mobile sources

High speed charge pump

Display interface embodiments are provided to capture various types of analog video signals and digitize them for presentation on advanced digital displays (e.g., computer displays and television displays). The embodiments include at least an error converter channel and a reference converter channel that can each amplify an analog input signal S with a fixed gain G and a programmed gain g and convert the amplified signal to a corresponding digital code. The embodiments also include a channel controller that is configured to conduct process steps that adjust the transfer function of the error converter channel to conform to (e.g., matches) the transfer function of the reference converter channel.

Growing community of inventors

Greensboro, NC, United States of America

Ralph David Moore, Jr