Intel Corporation

Real 3-D

Ati Technologies Ulc

Ati International Srl

Advanced Micro Devices Corporation

Ati Technologies Inc.

Ralph Clayton Taylor

Michael Mantor

Thomas A Piazza

Michael Andrew Mang

Val Gene Cook

Robert Scott Hartog

Jeffrey D Potter

John A Carey

Nuwan S Jayasena

Vineet Goel

Kevin John McGrath

Rex Eldon McCrary

Philip J Rogers

Daniel B Clifton

Sebastien Nussbaum

Mark M Leather

Thomas R Woller

Angel E Socarras

Stuart Krupnik

Steven Manno

R Scott Hartog

David Gotwalt

Methods and apparatus are described. A method includes an accelerated processing device running a process. When a maximum time interval during which the process is permitted to run expires before the process completes, the accelerated processing device receives an operating-system-initiated instruction to stop running the process. The accelerated processing device stops the process from running in response to the received operating-system-initiated instruction.

Preemptive context switching of processes on an accelerated processing device (APD) based on time quanta

A method and apparatus for providing rendering of subsections of screen space receives render commands associated with different screen subsections, such as from a command buffer populated by a coprocessor, and determines which screen section is currently being rendered by a rendering engine, or stated another way, which screen section the host processor wishes to have rendered, and evaluates screen subsection data that is associated with a received rendering command. The screen subsection data identifies a screen subsection for which the command refers. The method includes executing the command if it is determined that the command refers to a current screen section being rendered.

Display screen subsection rendering apparatus and method

An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.

Apparatus with redundant circuitry and method therefor

A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores it in cache memory. The data in the main memory and texture cache memory is organized in a manner to achieve large reuse of texels with a minimum of cache memory to minimize cache misses. The texture main memory stores a two dimensional array of texels, each texel having an address and one of N identifiers. The texture cache memory has addresses partitioned into N banks, each bank containing texels transferred from the main memory that have the corresponding identifier. A cache controller determines which texels need to be transferred from the texture main memory to the texture cache memory and which texels are currently in the cache using a least most recently used algorithm. By labeling the texture map blocks (double quad words), a partitioning scheme is developed which allow the cache controller structure to be very modular and easily realized. The texture cache arbiter is used for scheduling and controlling the actual transfer of texels from the texture main memory into the texture cache memory and controlling the outputting of texels for each pixel to an interpolating filter from the cache memory.

3-D rendering texture caching scheme

Method and apparatus for rendering texture to an object to be displayed on a pixel screen display. This technique makes use of linear interpolation between perspectively correct texture address to calculate rates of change of individual texture addresses components to determine a selection of the correct LOD map to use and intermediate texture addresses for pixels of the object between the perspectively correct addresses. The method first determines perspectively correct texture address values associated with four corners of a predefined span or grid of pixels. Then, a linear interpolation technique is implemented to calculate a rate of change of texture address components in the screen x and y directions for pixels between the perspectively bound span corners. This linear interpolation technique is performed in both screen directions to thereby create a potentially unique level of detail value for each pixel, which is then used as an index to select the correct pre-filtered LOD texture map. When mapping an individually determined LOD value per pixel, the effect of producing undesirable artifacts that may appear if a single LOD for an entire span or polygon is used, is obviated.

Method and apparatus for effective level of detail selection

A computation module and/or geometric engine for use in a video graphics processing circuit includes memory, a computation engine, a plurality of thread controllers, and an arbitration module. The computation engine is operably coupled to perform an operation based on an operation code and to provide a corresponding result to the memory as indicated by the operation code. Each of the plurality of thread controllers manages at least one corresponding thread of a plurality of threads. The plurality of threads constitutes an application. The arbitration module is coupled to the plurality of thread controllers and utilizes an application specific prioritization scheme to provide operation codes from the plurality of thread controllers to the computation engine such that idle time of the computation engine is minimized. The prioritization scheme prioritizes certain threads over other threads such that the throughput through the computation module is maximized.

Geometric engine including a computational module for use in a video graphics controller

A configurable vertex blending circuit that allows both morphing and skinning operations to be supported in dedicated hardware is presented. Such a configurable vertex blending circuit includes a matrix array that is used for storing the matrices associated with the various portions of the vertex blending operations. Vertex data that is received is stored in an input vertex buffer that includes multiple position buffers such that the multiple positions associated with morphing operations can be stored. Similarly, the single position typically associated with skinning operations can be stored in one of the position buffers. The input vertex buffer further stores blending weights associated with the various component operations that are included in the overall vertex blending operation. An arithmetic unit, which is configured and controlled by a transform controller, performs the calculations required for each of a plurality of component operations included in the overall vertex blending operation. The results of each of these component operations are then combined to produce a blended vertex.

Configurable vertex blending circuit and method therefore

Pixel engine

A method and system for rendering a feature, such as a line, for display on an array of pixels. With this method, the line is identified on the pixel array, the line is expanded into a polygon, and color values are determined for the pixels within the polygon. Also, an antialiasing region is identified in the polygon, and blend values are computed for the pixels in this antialiasing region. Then, the color values determined for the pixels in the antialiasing region are modified as a function of these computed blend values. The pixels in the antialiasing region may then be shown at their modified color values, while the pixels that are in the polygon but not in the antialising region may be shown at their original determined color value. Preferably, the blend values for the pixels in the antialiasing region are calculated as a function of the locations of the pixels in that region. For example, the blend value for each of these pixels may be calculated as a function of four values, each one representing the Manhattan distance from the pixel to a respective one of the edges of the polygon. Also, preferably the antialiasing region has a uniform width, and this region extends inward from side edges and outward from end edges of the formed polygon.

Methods and systems for rendering line and point features for display

A computationally efficient method for minimizing the visible effects of texture LOD transitions across a polygon. The minimization is accomplished by adding a dithering offset value to the LOD value computed for each pixel covered by a graphics primitive to produce a dithered pixel LOD value. The dithering offsets mat be generated from a table look-up based on the location of the pixel within a span of pixels. The dithered pixel LOD value is used to as an index in the selection of a single LOD texture map from which a textured pixel value is retrieved. The range of dithering offset values can be adjusted by modulating the values in the table look-up.

Method and apparatus for texture level of detail dithering

A rasterizer comprised of a bounding box calculator, a plane converter, a windower, and incrementers. For each polygon to be processed, a bounding box calculation is performed which determines the display screen area, in spans, that totally encloses the polygon and passes the data to the plane converter. The plane converter also receives as input attribute values for each vertex of the polygon. The plane converter computes planar coefficients for each attribute of the polygon, for each of the edges of the polygon. The plane converter unit computes the start pixel center location at a start span and a starting coefficient value at that pixel center. The computed coefficients also include the rate of change or gradient, for each polygon attribute in the x and y directions, respectively. The plane converter also computes line coefficients for each of the edges of the polygon. Line equation values are passed through to the windower where further calculations allow the windower to determine which spans are either covered or intersected by the polygon. The incrementers receive the span coverage data from the windower in addition to receiving planar coefficient values from the plane converter. The incrementers utilize the data from both the windower and plane converter to walk or traverse the polygon in those intersected spans, pixel by pixel. As the incrementer visits each pixel, vertex attribute values are interpolated to each pixel.

Growing community of inventors

Deland, FL, United States of America

Ralph Clayton Taylor