International Business Machines Corporation

Ralph C Mitchell

Robert Spencer Horton

Gerald Bernard Long

Shing Chou Pi

Walter G Temnycky

A programmable display controller allows reconfiguration of bit plane memory and video output connections based upon the type of display device employed. The display controller allows for the definition of multiple bit planes when the display device supports color or multiple gray shades. Simultaneous storage of images to all defined planes is accomplished through the use of multi-store logic. Multi-store logic transforms a data stream defining foreground and background portions of an image within a given display area into a form that can be simultaneously written to the bit planes as required to create the necessary output. Under processor control, a video palette may be loaded to ensure that display output signals are routed to the correct connector pins. The routing of particular signals to particular pins is reconfigured through the selection and loading of the applicable video palette. Video connector leads are connected to the palette generated data signals or to electrical ground by means of reconfigurable jumpers. The number of bit planes and display pages can be readily modified with a multi-mode controller translating the selected mode into the required bit plane memory control signals.

Programmable multi-format display controller

In this programmable logic array (PLA), internal array lines are shared by several sets of input array lines. Each set of input lines operates on a separate time phase. This PLA construction is denser than some other arrangements of multiple PLAs, and some of its components are reduced in number as compared with multiple independent PLAs for the same functions. A new pipelined multiplier is disclosed as one application for the PLA of this invention. In another application for this PLA, the array lines are shared where the array locations that are otherwise required for don't care states have been eliminated and a denser construction is provided.

PLA With time division multiplex feature for improved density

This specification describes arrays for performing logic functions. In these arrays input variables are placed on a series of parallel input lines that intersect a number of parallel output lines in a grid of intersections. Field effect devices at these intersections have their gate terminals connected to one of the input lines and their source terminal connected to one of the output lines and through a load device to a source of potential. The drain terminals of these devices are either unconnected, connected directly to ground or connected to ground through one of two switching devices. The devices with unconnected drains are inoperative. The devices with their drains connected directly to ground are operative at all times. While the devices connected to ground through one of the switches are operative only when the switch is closed. The array can be time shared by two different logic functions by having one or the other of the switches off at any given time.

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Kingston, NY, United States of America

Ralph C Mitchell