Infineon Technologies Ag

Infineon Technologies Austria Ag

Ralf Wombacher

Joachim Mahler

Petteri Palm

Thorsten Scharf

Khalil Hosseini

Horst Theuss

Franz-Peter Kalz

Joachim Voelter

Ralf Otremba

Ivan Nikitin

Alexander Heinrich

Edmund Riedl

Stefan Landau

Stefan Paulus

Anton Prueckl

Bernd Betz

Thomas Wowra

Dieter Lachman

An electronic module is disclosed. In one example, the electronic module includes a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer. The first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.

Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate

Electronic module, which comprises a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer, wherein the first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.

Electronic module (), which comprises a first substrate (), a first dielectric layer () on the first substrate (), at least one electronic chip (), which is mounted with a first main surface () directly or indirectly on partial region of the first dielectric layer (), a second substrate () over a second main surface () of the at least one electronic chip (), and an electrical contacting () for the electric contact of the at least one electronic chip () through the first dielectric layer (), wherein the first adhesion layer () on the first substrate () extends over an area, which exceeds the first main surface ().

A chip package is provided. The chip package may include an electrically conductive carrier; at least one first chip including a first side and a second side opposite of the first side, with its second side being electrically contacted to the electrically conductive carrier; an insulating layer over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip; at least one second chip arranged over the insulating layer and next to the first chip; encapsulating material over the first chip and the second chip; and electrical contacts which extend through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.

Chip package and chip assembly

A sensor package is disclosed. One embodiment provides a sensor device having a carrier, a semiconductor sensor mounted on the carrier and an active surface. Contact elements are electrically connecting the carrier with the semiconductor sensor. A protective layer made of an inorganic material covers at least the active surface and the contact elements.

Sensor package

A method of manufacturing a chip package is provided. The method may include electrically contacting at least one first chip, the first chip including a first side and a second side opposite the first side, with its second side to an electrically conductive carrier. An insulating layer is formed over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip. At least one second chip is arranged over the insulating layer. An encapsulating material is formed over the first chip and the second chip. Electrical contacts are formed through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.

Method of manufacturing a chip package, chip package, method of manufacturing a chip assembly and chip assembly

The semiconductor chip package comprises a carrier, a semiconductor chip comprising a first main face and a second main face opposite to the first main face, chip contact elements disposed on one or more of the first or second main faces of the semiconductor chip, an encapsulation layer covering the first main face of the semiconductor chip, the encapsulation layer comprising a first main face facing the carrier and a second main face remote from the carrier, first contact elements disposed on the second main face of the encapsulation layer, each one of the first contact elements being connected to one of the chip contact elements, and second contact elements disposed on the first main face of the encapsulation layer, each one of the second contact elements being connected to one of the chip contact elements.

Semiconductor chip package

A method of manufacturing a semiconductor device includes providing a transfer foil. A plurality of semiconductor chips is placed on and adhered to the transfer foil. The plurality of semiconductor chips adhered to the transfer foil is placed over a multi-device carrier. Heat is applied to laminate the transfer foil over the multi-device carrier, thereby accommodating the plurality of semiconductor chips between the laminated transfer foil and the multi-device carrier.

Semiconductor device and method of manufacturing thereof

A chip arrangement is provided, the chip arrangement including: a first chip carrier; a second chip carrier; a first chip electrically connected to the first chip carrier; a second chip disposed over the first chip carrier and electrically insulated from the first chip carrier; and a third chip electrically connected to the second chip carrier; wherein at least one of the first chip and the second chip is electrically connected to the third chip.

Chip arrangement, a method for forming a chip arrangement, a chip package, a method for forming a chip package

This application relates to a semiconductor device, the semiconductor device comprising a metal carrier, an insulating foil partially covering the metal carrier, a first chip attached to the metal carrier over the insulating foil, and a second chip attached to the metal carrier over a region not covered by the insulating foil.

Electronic device and method of manufacturing same

A semiconductor device includes semiconductor device components, an adhesion promoter structure and a plastic housing composition. The semiconductor device components are embedded in the plastic housing composition with the adhesion promoter structure being disposed between the device components and the housing composition. The adhesion promoter structure includes first and second adhesion promoter layers. The first layer includes metal oxides. The metal oxides being silicates of a reactive compound composed of oxygen and organometallic molecules. The second layer includes at least one polymer.

Semiconductor device with semiconductor device components embedded in a plastic housing composition

A semiconductor device and a method for producing it, and the use of the electrospinning method is disclosed. In one embodiment, delamination of the plastic housing composition from the circuit carrier can occur under loading, which can lead to the failure of the semiconductor device. For better adhesion, an adhesion-promoting layer having fibers applied by electrospinning is arranged between the circuit carrier and the plastic housing composition.

Growing community of inventors

Burglengenfeld, Germany

Ralf Wombacher