Infineon Technologies Ag

Qimonda Ag

Adesto Technologies Corporation

Altis Semiconductor, Snc

Altis Semiconductor

Ralf Symanczyk

Thomas Happ

Michael Kund

Cay-Uwe Pinnow

Thomas Roehr

Klaus-Dieter Ufert

Josef Willer

Franz Kreupl

Martin Gutsche

Ulrich Karl Klostermann

Ulrike Gruening-von Schwerin

Corvin Liaw

Bernhard Ruf

Petra Majewski

Dieter Andres

Paul-Henri Albarede

Christelle Albarede, Legal Representative

Rainer Bruchhaus

Christian Ruester

A method for operating a resistivity changing memory including applying a programming voltage to a resistivity changing memory cell to define a programmed state and applying a refresh voltage to the resistivity changing memory cell for maintaining the programmed state of the resistivity changing memory cell. In one embodiment, the refresh voltage is less than the programming voltage.

Method for operating an integrated circuit having a resistivity changing memory cell

According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element.

Integrated circuit

An integrated circuit with memory having a current limiting switch includes a memory cell having a programmable resistivity layer and a writing line. A switch is arranged between the resistivity layer and the writing line. The switch includes a control input connected to a select line. The switch is configured to limit a current through the resistivity layer for a write operation.

Integrated circuit with memory having a current limiting switch

An integrated semiconductor memory includes a storage medium () arranged between two electrodes (), which storage medium may be a phase change medium, for example. The storage medium () can be put into a first state or a second state by means of an electric current, as a result of which an item of information can be stored. According to embodiments of the invention, a layer plane (L) is provided in which impurity particles made from a material () are embedded, as a result of which the current density in the storage medium is locally increased and the programming current required for reprogramming is reduced. As a result, the current consumption of memory elements containing a phase change medium is reduced, so that for the first time they can be embodied with minimal feature size, together with other components such as transistors, and integrated into a single semiconductor circuit and no longer have to be arranged in separate subcircuits.

Integrated circuit having a resistive memory

The invention relates to a memory component having memory cells based on an active solid electrolyte material which can be changed in terms of its resistance value. The active solid electrolyte material is embedded between a bottom and top electrode, can be switched between an on state with a low resistance and an off state with a high resistance by comparison therewith by application of a suitable electric field between said electrodes. A resistance material is embedded in parallel with the solid electrolyte material between the electrodes.

Memory component with memory cells having changeable resistance and fabrication method therefor

A retention test system and method for resistively switching memory devices is disclosed. One embodiment provides a plurality of memory cells configured to be changed over between a first state of high electrical resistance and a second state of low electrical resistance, wherein the system is configured to apply a bias voltage to at least one memory cell of the memory device to be tested.

Retention test system and method for resistively switching memory devices

According to one embodiment of the present invention, a CBRAM cell includes a solid electrolyte block having at least three solid electrolyte contacting areas, electrodes electrically connected to the solid electrolyte contacting areas, wherein conductive paths are formable, erasable or detectable within the solid electrolyte block by applying voltages between the solid electrolyte contacting areas using the electrodes as voltage suppliers, and wherein the contacting areas are spatially separated from each other such that conductive paths starting from different solid electrolyte contacting areas or ending at different solid electrolyte contacting areas do not overlap each other.

CBRAM cell and CBRAM array, and method of operating thereof

A memory cell having a programmable solid state electrolyte layer, a writing line and a controllable switch that is arranged between the solid state electrolyte layer and the writing line. The controllable switch has a control input that is connected with a selecting line and the switch also has a limiting element that limits a current through the solid state electrolyte layer to a predetermined amount of electric charge for a write operation.

Integrated circuit having a memory cell

The invention relates to a chip card security device, a procedure to be used in securing a chip card, as well as a chip card (), comprising:

Chip card and chip card security device

A memory cell arrangement has a plurality of memory cells of the CBRAM type and a programming apparatus, the memory cells being arranged along bit lines and each bit line having a programming apparatus. The invention provides for the programming apparatus to comprise a charge storage device and a switchable charging apparatus. The inventive method for programming memory cells of the CBRAM type is carried out in such a manner that, a given quantity of an electrical charge is stored in a charge storage device, and the stored quantity of electrical charge is transferred to the memory cell to be programmed.

Memory having CBRAM memory cells and method

According to the invention, a memory system, and a process for controlling a memory component, to achieve different kinds of memory characteristics on one and the same memory component, is provided, the process comprising the steps:

Memory system and process for controlling a memory component to achieve different kinds of memory characteristics on one and the same memory component

The object of providing a method for manufacturing solid body electrolyte memory cells or CB memory cells, respectively, which is suited for the simplified manufacturing of highly dense arrays with crosspoint architecture is solved by the present invention in that the solid body electrolyte memory cells are manufactured by self-aligned etching of the word lines that constitute simultaneously the top electrodes of the memory cells, and of the CB memory cells themselves. An advantage of the inventive method consists in that no via lithography is required, so that the manufacturing method is easier to perform, less expensive, and yields reliable results.

Manufacturing method with self-aligned arrangement of solid body electrolyte memory cells of minimum structure size

A method is describe for fabricating memory components including memory cells based on an active material of an active layer, the phase state of which can be changed and which is enclosed between a bottom electrode and a top electrode. To reduce the current intensity of the programming current and the erase current required for programming and erasing of the memory element and therefore the quantity of heat which is required to change the phase state, a nanoporous aluminium oxide layer is used as a mask during the production of the active layer or the interface with the electrodes. The nanoporous aluminium oxide layer can be used as a positive mask, as a negative mask, or used directly as an insulating current aperture. The contact surface between electrode and active layer can be set in virtually any desired form by varying the process parameters of the aluminium oxide mask. Since the typical cell area of the memory cell is significantly larger than the mean diameter of the nanopores, a good homogeneity and reproducibility of the contacts results from a production engineering standpoint.

Fabricating memory components (PCRAMS) including memory cells based on a layer that changes phase state

The invention relates to a memory cell for providing an information item, having a memory element, which has a PMC resistance component with a solid electrolyte material. The solid electrolyte material may be put into a first state with a high electrical resistance and into a second state with a low electrical resistance. The memory element has a resistance element which is connected up to the PMC resistance component in such a way as to reduce the total resistance of the memory element in the first state.

Integrated circuit including memory cell for storing an information item and method

The invention relates to a PMC memory circuit comprising a PMC memory cell having a PMC component, the PMC component having a solid electrolyte with permanently introduced defects, so that the PMC component has a hysteresis with regard to its I-V characteristic curve with an upper and a lower current value branch, and a data retention unit, which, for storing a state to be stored, applies to the PMC component a center voltage or storage voltage at which the PMC component is operated, either in the upper current value branch of the hysteresis for the purpose of storing a first state or in the lower current value branch of said hysteresis for the purpose of storing a second state.

Growing community of inventors

Munich, Germany

Ralf Symanczyk