Infineon Technologies Ag

Qimonda Ag

Ralf Schledz

Peter Gregorius

Martin Streibl

Hermann Ruckerbauer

Thomas Rickes

Paul Wallner

Johannes Stecker

Georg Braun

Dominique Savignac

Christoph Steiner

Markus Schimper

Stephan Mechnig

Christian Weiss

Olaf Roesch

Zheng Gu

Embodiments relate to a control unit comprising a data input to receive wheel rotation data from each of a plurality of fixed wheel rotation sensors associated with a wheel of a vehicle and acceleration samples from a plurality of wheel units. The control unit includes a processor to localize each of the plurality of wheel units to a particular wheel of the vehicle from a joint processing of the wheel rotation data and the acceleration samples.

Tire localization systems and methods in tire pressure monitoring systems

Method and device for transmitting outgoing useful signals and an outgoing clock signal. Useful signals and a clock signal are transmitted from a transmitter via a first line pair and a second line pair to a receiver. A first useful signal is transmitted in the form of a modulated difference between the electrical potentials of the first line pair. A second useful signal is transmitted in the form of a modulated difference between the electrical potentials of the second line pair. The clock signal is transmitted in the form of a modulated difference between the average value of the potentials of the first line pair and the average value of the potentials of the second line pair.

Method and device for transmitting outgoing useful signals and an outgoing clock signal

A data receiver has a sampling unit connected to a data signal input and configured to sample a data signal amplitude and amplify the sampled data signal amplitude to a predetermined value, a sampling clock generator unit connected to the sampling unit and configured to predetermine a sampling clock for the sampling unit, an evaluation unit connected to the sampling unit and configured to determine the time duration required by the sampling unit for amplifying the sampled data signal amplitude to the predetermined value and evaluate the time duration determined, and a control unit connected to the evaluation unit and the sampling clock generator and configured to define the sampling clock on the basis of the evaluation of the time duration determined by the evaluation unit.

Data receiver with clock recovery circuit

A digital control loop and a method for clock generation. A control loop includes at least one phase detector configured to detect a phase shift of a feedback signal relative to a reference clock signal and output a correction signal on the basis of the phase shift detected. At least one control loop filter is configured to output, on the basis of the correction signal, a first control signal and a second control signal, the first control signal being substantially the same as the second control signal except that oscillations are suppressed in the second control signal. At least one first phase generator is configured to output a first clock signal on the basis of the first control signal and the first phase reference signal, wherein the first clock signal is transmitted at least partially as feedback signal to the phase detector. At least one second phase generator receives the second control signal and the first phase reference signal, wherein the second phase generator is functionally substantially the same as the first phase generator and is configured to output a second clock signal on the basis of the second control signal and the first phase reference signal.

Apparatus and method for avoiding steady-state oscillations in the generation of clock signals

A sensor circuit has a first input terminal, a second input terminal and an output terminal, a capacitive sensor connected between the first input terminal and the output terminal, a field-effect transistor coupled to the output terminal at one of a source and a drain terminal and coupled to the second input terminal at the other one of the source and drain terminals, and a driver implemented to set a potential at a control terminal of the field-effect transistor such that in sensor operation the field-effect transistor is operated in a sub-threshold voltage range.

Sensor circuit for measuring a measuring quantity

The invention provides a data handover unit for transferring data from a furst clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a selector stage operable to sample an incoming data stream with respect to the first clock signal; a second clock unit operable to supply a second clock signal; a storage unit coupled with the selector stage, wherein the storage unit has a first plurality of storage elements each of which is operable to store one bit of data of the sampled data stream, an output unit for parallelly reading out a fram of data from a second plurality of storage elements included in the first plurality of storage elements with respect to the second clock signal, wherein the selector stage is further operable to successively write the data bits of the sampled data stream into the first plurality of storage elements and to store the respective data bits of the sampled data stream in the respective storage elements until they were read out by the output unit.

Data handover unit for transferring data between different clock domains by parallelly reading out data bits from a plurality of storage elements

A semiconductor memory arrangement for operation in a data memory system with at least one semiconductor memory chip for the storage of user data includes a memory controller for control of the at least one semiconductor memory chip, and at least one unidirectional signal line bus for control and address signals connected with the memory controller and branching at least once. The at least once branching bus directly connecting at least one semiconductor memory chip with the memory controller and connecting the semiconductor memory chips among each other.

Semiconductor memory arrangement with branched control and address bus

A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory controller for control of the at least one semiconductor memory chip includes at least one unidirectional, serial signal line bus for control and address signals connected with the memory controller, directly connecting at least one semiconductor memory chip with the memory controller and serially connecting with each other the semiconductor memory chips among each other by 1-point-to-1-point connections.

Semiconductor memory array with serial control/address bus

A memory system and method is discussed. The memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.

Memory system and method of accessing memory chips of a memory system

A synchronous parallel/serial converter is disclosed. In one embodiment, the a synchronous parallel/serial converter that receives a parallel n-bit input signal and comprising a first shift register that receives an odd-numbered part of the input signal with a first load signal in synchronism with a clock signal having a clock rate half the clock rate of a system clock, and provides a serial output as a first one-bit signal sequence; a second shift register that receives an even-numbered part of the input signal with a second load signal synchronism with the clock signal and provides a serial output as a second one-bit signal sequence; and a fusion unit that fuses the first serial one-bit signal sequence synchronously with the clock signal and the second serial one-bit signal sequence in synchronism the clock signal to form a serial one-bit output signal.

Synchronous parallel/serial converter

The invention relates to a circuit for low noise, fully differential amplification. A feedback signal () is detected in a differential output step of the differential amplification circuit by means of a voltage distributor formed by a first feedback resistance () and a second feedback resistance (). A first output signal () is provided at a first output circuit node () and a second output signal () is provided at a second output circuit node (). The respective first and second output signals () or () form a full output signal which corresponds to an input signal formed by a first and a second input signal () or (). A load current (), an input current () and a reference current () are established by means of a load current source (), an input current source () and a reference current source (). A matching transistor () is used to adjust an adaptation between the load current source (), the input current source () and the reference current source (). A feedback signal () of the differential amplification circuit is compared with a reference voltage () in a reference step, and the load current () is mirrored in the differential input step, in a current mirror device.

Growing community of inventors

Zolling, Germany

Ralf Schledz