Infineon Technologies Ag

Qimonda Ag

Infineon Technologies North America Corp.

Giesecke+devrient Mobile Security Gmbh

Giesecke & Devrient Gmbh

Ralf Schedel

Thomas Hein

Wolfgang Anton Spirkl

Peter Gregorius

Hermann Ruckerbauer

Johannes Stecker

Thilo Schaffroth

Martin Maier

Jong-Hoon Oh

Markus Balb

Claus Dietze

Johannes Luyken

Daniel Albert

Markus Sexl

Frank Schäfer

Walter Fiessinger

Helmut Schuster

Cinkler Kalman

A method is provided for installing a security-relevant portion of an application made available by an application provider in a security element of a terminal. The terminal requests the application from the application provider and receives the application. Subsequently, the received security-relevant portion of the application is transmitted to a trustworthy instance administrating the security element. The trustworthy instance subsequently installs the security-relevant portion of the application in the security element.

Method for installing security-relevant applications in a security element of a terminal

Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.

Multi-port DRAM architecture for accessing different memory partitions

A system and method utilize a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated with a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, a plurality of memory devices may be arranged in a memory package in a stacked die memory configuration.

Method and system including plural memory controllers and a memory access control bus for accessing a memory device

A device or method for activating a memory, which includes receiving a select signal at the memory, receiving a plurality of address bits at the memory, determining whether the select signal is active, determining whether a first bit in the plurality of address bits has a first value, and activating the memory only if the select is active and the first bit has the first value.

Memory system

A circuit arrangement for a communication system for terminating a plurality of interfaces at a common bus and for generating a synchronization clock for synchronizing the bus is provided. In one aspect, a circuit arrangement for a communication system includes a first multiplexer controlled by a first control signal with a plurality of inputs corresponding to a plurality of transmission lines of the interfaces, a respective phase control unit, preceding each input of the first multiplexer, which derives a respective clock generator signal from a received signal of the corresponding transmission line, where the clock generator signal of one of the transmission lines is switched through as output signal of the first multiplexer in dependence on the first control signal, and a phase locked loop, at the inputs of which the output signal of the first multiplexer and a clock from a clock generator operated with an external crystal oscillator.

Circuit for generating clock pulses in a communications system

Growing community of inventors

Starnberg, Germany

Ralf Schedel