Infineon Technologies Austria Ag

Infineon Technologies Dresden Gmbh

Infineon Technologies Ag

Infineon Technologies Dresden Gmbh & Co . Kg

Eupec Europaeische Gesellschaft Fuer Leistungshalbleiter Mbh & Co. Kg

Ralf Rudolf

Rolf Weis

Dirk Priefert

Marko Lemke

Marc Strasser

Lincoln O'Riain

Karl-Heinz Gebhardt

Andreas Peter Meiser

Till Schloesser

Uwe Wahl

Jens Schneider

Herwig Wappis

Knut Stahrenberg

Christian Schippel

Felix Braun

Lars Müller-Meskamp

Andreas Greiner

Heiko Aßmann

Viktor Boguszewicz

Rolf Buckhorst

Marcus Dankelmann

Frank Michalzik

Stefan Doering

Annett Winzer

Karsten Friedrich

Thomas Künzig

Udo Goetschkes

A semiconductor device includes a semiconductor layer with an inner portion, an outer portion laterally surrounding the inner portion, and a transition portion laterally surrounding the inner portion and separating the inner portion and the outer portion. A first electric element includes a first doped region formed in the inner portion and a second doped region formed in the outer portion. The first electric element is configured to at least temporarily block a voltage applied between the first doped region and the second doped region. A trench isolation structure extends from a first surface into the semiconductor layer and segments at least one of the inner portion, the transition portion, and the outer portion.

High-voltage semiconductor device

A semiconductor device includes an insulator layer and a semiconductor layer formed on the insulator layer. The semiconductor layer includes a first region of a first conductivity type, a second region of a second conductivity type, and a lightly doped extension region of the first conductivity type separating the first region and the second region along a lateral x-axis. A dielectric structure laterally surrounds the semiconductor layer. At least one of the first region and the lightly doped extension region is formed at a distance to the dielectric structure along a lateral y-axis orthogonal to the x-axis. Along the x-axis and between the second region and the first region, a lateral extension of the semiconductor layer along the y-axis increases with increasing distance to the second region.

Semiconductor-on-insulator device with lightly doped extension region

An electronic circuit includes: a drive circuit having an output coupled to a control node of a first electronic switch; a switch circuit with second electronic switches, load paths of the second electronic switches being connected in series, and the switch circuit being connected between a first load node of the first electronic switch and a reference node; and a level shifter coupled between a first signal input and an input of the drive circuit and including cascaded level shifter cells. Each level shifter cell includes a signal input and output, and first and second supply nodes. Each level shifter cell is associated with a respective second electronic switch. The first supply node of each level shifter cell is coupled to a first load node of the associated second electronic switch, and the second supply node is coupled to a second load node of the associated second electronic switch.

Electronic circuit with several electronic switches connected in series and a drive circuit

A semiconductor device includes a semiconductor substrate of a first conductivity type. A first semiconductor layer of a second conductivity type is on the semiconductor substrate. A buried semiconductor layer of the second conductivity type is on the first semiconductor layer. A second semiconductor layer of the second conductivity type is on the buried semiconductor layer. A trench extends through each of the second semiconductor layer, the buried semiconductor layer, and the first semiconductor layer, and into the semiconductor substrate. An insulating structure lines walls of the trench. A conductive filling in the trench is electrically coupled to the semiconductor substrate at a bottom of the trench.

Semiconductor device having a buried layer

In various embodiments, a method is provided. The method may include forming a buried electrically charged region at a predefined position in a first layer in such a way that the buried electrically charged region generates an electric field having a lateral inhomogeneous field distribution above the first layer, and forming a second layer above the first layer using the field distribution in such a way that a structure of the second layer correlates with the position of the buried electrically charged region.

Method for producing a self-aligning masking layer

A method of forming a power semiconductor device includes providing a semiconductor layer of a first conductivity type extending to a first side and having a first doping concentration of first dopants providing majority charge carriers of a first electric charge type in the layer, and forming a deep trench isolation including forming a trench which extends from the first side into the semiconductor layer and includes, in a vertical cross-section perpendicular to the first side, a wall, forming a compensation semiconductor region of the first conductivity type at the wall and having a second doping concentration of the first dopants higher than the first doping concentration, and filling the trench with a dielectric material. The amount of first dopants in the compensation semiconductor region is such that a field-effect of fixed charges of the first electric charge type which are trapped in the trench is at least partly compensated.

Method for forming a power semiconductor device and a power semiconductor device

A method for forming an insulation structure in a semiconductor body includes forming a trench extending from a first surface into a semiconductor body, the trench having a first width in a horizontal direction of the semiconductor body, and forming a void spaced apart from the first surface in a vertical direction of the semiconductor body, the void having a second width in a horizontal direction that is greater than the first width, wherein the trench and the void are arranged adjacent to each other in a vertical direction.

Insulation structure formed in a semiconductor substrate and method for forming an insulation structure

A semiconductor device includes an electrode arranged on a main surface of a semiconductor body and an insulating structure insulating the electrode from the semiconductor body. The insulating structure includes in a vertical cross-section a gate dielectric portion forming a first horizontal interface at least with a drift region of the device and having a first maximum vertical extension between the first horizontal interface and the electrode, and a field dielectric portion forming with the drift region second, third and fourth horizontal interfaces. The second through fourth horizontal interfaces are arranged below the main surface. The third horizontal interface is arranged between the second and fourth horizontal interfaces. A second maximum vertical extension is larger than the first maximum vertical extension and a third maximum vertical extension is larger than the second maximum vertical extension. The electrode only partially overlaps the third horizontal interface.

Semiconductor device with an insulating structure for insulating an electrode from a semiconductor body

A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension.

Lateral semiconductor device and manufacturing method therefor

A semiconductor device includes a first transistor with a first drift zone, and a plurality of second transistors, each second transistor comprising a source region, a drain region and a gate electrode. The second transistors are electrically coupled in series to form a series circuit that is electrically coupled to the first transistor, the first and the plurality of second transistors being at least partially disposed in a semiconductor substrate including a buried doped layer, wherein the source or the drain regions of the second transistors are disposed in the buried doped layer.

Semiconductor device and method for manufacturing a semiconductor device

An SOI semiconductor component comprises a semiconductor substrate having a basic doping, a dielectric layer arranged on the semiconductor substrate, and a semiconductor layer arranged on the dielectric layer. The semiconductor layer includes a drift zone of a first conduction type, a junction between the drift zone and a further component zone which is configured in such a way that a space charge zone is formed in the drift zone when a reverse voltage is applied to the junction, and a terminal zone adjacent to the drift zone. A first terminal electrode is connected to the further component zone, and a second terminal electrode is connected to the terminal zone. In the semiconductor substrate a first semiconductor zone is doped complementarily with respect to a basic doping of the semiconductor substrate, and the first terminal electrode is connected to the first semiconductor zone. A rectifier element is connected between the first terminal electrode and the first semiconductor zone.

Lateral SOI component having a reduced on resistance

A lateral semiconductor element ( ) in thin-film SOI technology comprises an insulator layer ( ) which rests on a substrate ( ) and is buried under a thin silicon film ( ), on top of which the source, or anode, contact ( ) and the drain, or cathode, contact ( ) are mounted. The anode contact ( ) and the cathode contact ( ) each lie over separate shield regions ( ) within substrate ( ), with the anode contact ( ) being electrically connected with substrate ( ).

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Dresden, Germany

Ralf Rudolf