Globalfoundries Inc.

Advanced Micro Devices Corporation

Globalfoundries U.S. Inc.

Marvell International Limited

Ralf Richter

Jan Hoentschel

Stefan Flachowsky

Peter Javorka

Jens Heinrich

Kai Frohberg

Joerg Hohage

Sven Beyer

Carsten Peters

Torsten Huisinga

Heike Salz

Andy C Wei

Markus Lenski

Matthias Schaller

Robert Seidel

Ran Yan

Martin Gerhardt

Martin Mazur

Holger S Schuehrer

Michael Finken

Juergen Boemmels

Thomas Melde

Stephan Kronholz

Frank Feustel

Thomas Werner

Frank Seliger

Nicolas Sassiat

Volker Grimm

Stefan Dünkel

Stefan Duenkel

Thomas Foltyn

Thorsten E Kammler

Matthias Lehr

Uwe Griebenow

Roman Boschke

Hartmut Ruelke

Thomas Feudel

Anthony Mowry

Carsten Grass

Ronny Pfuetzner

Jan Paul

Yu-Teh Chiang

Manfred Horstmann

Maciej Wiatr

Juergen Faul

Martin Trentzsch

Ralf Illgen

Gunter Grasshoff

Tom Herrmann

Casey Scott

Katrin Reiche

Andreas Ott

Eckhard Langer

Tobias Letz

Elke Erben

Johannes F Groschopf

Zhi-Yuan Wu

Ming-Cheng Chang

Hans-Jürgen Thees

Sven Mueller

Peter Krottenthaler

Katja Steffen

Johannes Müller

Ronald Naumann

Ronny Pfutzner

Jana Schlott

Andrey Zakharov

Soeren Jansen

Sandhya Chandrashekhar

Manfred Heinz

Sylvio Mattick

Jochen Willi Poth

Ellen Claus

Jochen Klais

A nonvolatile memory device is provided, the device comprising a ferroelectric memory capacitor arranged over a first active region contact of a first transistor and a gate contact of a second transistor, whereby the ferroelectric memory capacitor at least partially overlaps a gate of the first transistor.

Ferroelectric nonvolatile memory device and integration schemes

A non-volatile memory (NVM) structure includes a first memory device including: a first inter-poly dielectric defined by an isolation layer over a first semiconductor layer over an insulator layer (SOI) stack over a bulk semiconductor substrate, a first tunneling insulator defined by the insulator layer, a first floating gate defined by the semiconductor layer of the SOI stack, and a first channel region defined in the bulk semiconductor substrate between a source region and a drain region. The memory device may also include a control gate over the SOI stack, an erase gate over a source region in the bulk substrate, and a bitline contact coupled to a drain region in the bulk substrate. The NVM structure may also include another memory device similar to the first memory device and sharing the source region.

Non-volatile memory structure using semiconductor layer as floating gate and bulk semiconductor substrate as channel region

A memory device structure includes a wafer substrate and a magnetic tunnel junction (MTJ) positioned above an upper surface of the wafer substrate. The MTJ includes a first magnetic layer, a second magnetic layer laterally adjacent the first magnetic layer, and a nonmagnetic layer interposed between the first and second magnetic layers, wherein the first magnetic layer, the nonmagnetic layer and the second magnetic layer comprise a substantially vertical layer stack that extends along a first direction that is substantially perpendicular to the upper surface of the wafer substrate. A first contact is electrically coupled to the first magnetic layer and a second contact is electrically coupled to the second magnetic layer.

Memory device structure

A semiconductor structure includes a plurality of pairs of nonvolatile memory cells arranged in a row, an edge cell positioned adjacent to the pairs of nonvolatile memory cells, and first, second, third, and fourth gates. Each pair of nonvolatile memory cells includes first and second nonvolatile memory cells. The first and second gates extend across the first nonvolatile memory cells, the second gate partially overlapping the first gate, and the third and fourth gates extend across the second nonvolatile memory cells, the fourth gate partially overlapping the third gate. Each of the first, second, third, and fourth gates has an end portion that is positioned in the edge cell, and the edge cell includes a protection layer that is positioned over the end portions of the first, second, third, and fourth gates and covers an end face of the second and fourth gates.

Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell

A semiconductor device includes a plurality of spaced apart fins, a dielectric material layer positioned between each of the plurality of spaced apart fins, and a common gate structure positioned above the dielectric material layer and extending across the fins. A continuous merged semiconductor material region is positioned on each of the fins and above the dielectric material layer, is laterally spaced apart from the common gate structure, extends between and physically contacts the fins, has a first sidewall surface that faces toward the common gate structure, and has a second sidewall surface that is opposite of the first sidewall surface and faces away from the common gate structure. A stress-inducing material is positioned in a space defined by at least the first sidewall surface, opposing sidewall surfaces of an adjacent pair of fins, and an upper surface of the dielectric material layer.

Three-dimensional transistor with improved channel mobility

In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.

Transistor element including a buried insulating layer having enhanced functionality

An integrated circuit product includes a silicon-on-insulator (SOI) substrate and a flash memory device positioned in a first area of the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulating layer positioned above the semiconductor bulk substrate, and a semiconductor layer positioned above the buried insulating layer, and the flash memory device includes a flash transistor device and a read transistor device. The flash transistor device includes a floating gate, an insulating layer positioned above the floating gate, and a control gate positioned above the insulating layer, wherein the floating gate includes a portion of the semiconductor layer. The read transistor device includes a gate dielectric layer positioned above the semiconductor bulk substrate and a read gate electrode positioned above the gate dielectric layer.

Flash memory device

The present disclosure provides storage elements, such as storage transistors, wherein at least one storage mechanism is provided on the basis of a ferroelectric material formed in the buried insulating layer of an SOI transistor architecture. In further illustrative embodiments, one further storage mechanism is implemented in the gate electrode structure, thereby providing increased overall information density. In some illustrative embodiments, the storage mechanism in the gate electrode structure is provided in the form of a ferroelectric material.

Non-volatile transistor element including a buried ferroelectric material based storage mechanism

Methods of forming a buffer layer to imprint ferroelectric phase in a ferroelectric layer and the resulting devices are provided. Embodiments include forming a substrate; forming a buffer layer over the substrate; forming a ferroelectric layer over the buffer layer; forming a channel layer over the ferroelectric layer; forming a gate oxide layer over a portion of the channel layer; and forming a gate over the gate oxide layer.

Ferro-FET device with buried buffer/ferroelectric layer stack

Methods of forming a device structure for a field-effect transistor and device structures for a field-effect transistor. A first gate dielectric layer is formed on a semiconductor layer in a first area. A hardmask layer is formed on the first gate dielectric layer in the first area of the semiconductor layer. A gate stack layer is formed on the semiconductor layer in a second area and on the hardmask layer in the first area of the semiconductor layer. The hardmask layer separates the gate stack layer from the first gate dielectric layer on the first area of the semiconductor layer.

Logic and flash field-effect transistors

In illustrative embodiments disclosed herein, a logic element may be provided on the basis of a non-volatile storage mechanism, such as ferroelectric transistor elements, wherein the functional behavior may be adjusted or programmed on the basis of a shift of threshold voltages. To this end, a P-type transistor element and an N-type transistor element may be connected in parallel, while a ferroelectric material may be used so as to establish a first polarization state resulting in a first functional behavior and a second polarization state resulting in a second different functional behavior. For example, the logic element may enable a switching between P-type transistor behavior and N-type transistor behavior depending on the polarization state.

Programmable logic elements and methods of operating the same

A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, forming a first transistor device on and in the SOI substrate in a logic area of the SOI substrate, removing the semiconductor layer and the buried insulation layer from a memory area of the SOI substrate, forming a dielectric layer on the exposed semiconductor bulk substrate, forming a floating gate layer on the first dielectric layer, forming an insulating layer on the floating gate layer and forming a control gate layer on the insulating layer, wherein an upper surface of the floating gate layer is substantially at the same height level as an upper surface of the semiconductor layer remaining in the logic area.

Semiconductor device comprising a floating gate flash memory device

The present disclosure provides a method of forming a capacitor structure and a capacitor structure. A semiconductor-on-insulator substrate is provided comprising a semiconductor layer, a buried insulating material layer and a semiconductor substrate material. A shallow trench isolation structure defining a first active region on the SOI substrate is formed, the first active region having a plurality of trenches formed therein. Within each trench, the semiconductor substrate material is exposed on inner sidewalls and a bottom face. A layer of insulating material covering the exposed semiconductor substrate material is formed, and an electrode material is deposited on the layer of insulating material in the first active region.

Method of forming a capacitor structure and capacitor structure

A method includes providing a semiconductor structure having a gate structure arrangement provided over a substrate. The gate structure arrangement includes one or more first gate structures and has a first sidewall and a second sidewall on opposite sides of the gate structure arrangement. A second gate structure is formed including a first portion at the first sidewall, a second portion at the second sidewall and a third portion connecting the first and second portions. Each of the first, second and third portions of the second gate structure includes a first part over the gate structure arrangement and a second part over a portion of the substrate adjacent the gate structure arrangement. After the formation of the second gate structure, one or more sections of the second gate structure are removed, wherein the first and second portions of the second gate structure are separated from each other.

Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell and method for the formation thereof

A method of manufacturing a flash memory device is provided including providing a silicon-on-insulator (SOI) substrate, in particular, a fully depleted silicon-on-insulator (FDSOI) substrate, comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer and forming a memory device on the SOI substrate. Forming the flash memory device on the SOI substrate includes forming a flash transistor device and a read transistor device.

Growing community of inventors

Dresden, Germany

Ralf Richter