Infineon Technologies Ag

Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Siemens Aktiengesellschaft

Infineon Technologies LLC

Ralf Peter Brederlow

Roland Thewes

Christian Pacha

Tobias Bernhard Fritz

Baher S Haroun

Thomas Schulz

Wolfgang Rösner

Jessica Hartwich

Werner Weber

Michael Szelong

Swaminathan Sankaran

Bradley Allen Kramer

James Robert Todd

Peter Wongeun Chung

Rüdiger Kuhn

Jeongwook Koh

Oscar Miguel Guillen-Hernandez

Umidjon Nurmetov

Francesco Silvio Santoro

Vadim Valerievich Ivanov

Steven Craig Bartling

Neil Gibson

Marc Tiebout

Ernst Georg Muellner

Christian Paulus

Johannes Gerber

Jose Antonio Vieira Formenti

Martin Staebler

Klaus Von Arnim

Jörg Berthold

Guido Stromberg

Bjoern Oliver Eversmann

Bjorn-Oliver Eversmann

Peter Fundaro

Marcin Augustyniak

Jiri Panacek

Ivo Koren

Sylvain Briole

Thomas Strum

Ernst Gerog Muellner

Niel Gibson

In described examples, a circuit includes an analog frontend arranged to generate an analog stress compensating signal in response to a to-be-compensated analog signal and a first-axis stress sensing signal. The analog frontend can comprise a first precision component (e.g.,) arranged on a piezoelectric material and arranged to generate the to-be-compensated analog signal that is affected by a stress exerted in the piezoelectric material and a directional stress sensor arranged on the piezoelectric material and coupled to the first precision component. The directional stress sensor is arranged to generate the first-axis sensing signal in response to a longitudinal resultant of a stress exerted in the piezoelectric material. A compensating circuit is arranged to generate a compensated output signal in response to the compensating analog signal and to-be-compensated analog signal.

On-substrate mechanical stress sensing and compensation

An integrated circuit comprises a semiconductor substrate having a surface. A lateral resistor is arranged in a first plane parallel to the surface of the substrate. A vertical reference resistor comprises a layer arranged in a second plane parallel to the surface of the substrate and deeper than the first plane. This layer is doped to promote current flow in the second plane. The vertical reference resistor further comprises a first trench and a second trench coupled between the layer and the surface of the substrate. The first and second trenches are arranged in a vertical direction orthogonal to the first and the second planes and are doped to impede current flow in the vertical direction. A cross-section of the first and second trenches is two-fold rotationally symmetric around the vertical direction, and the lateral resistor and the first and second trenches have the same temperature coefficient.

Tracking temperature compensation of an x/y stress independent resistor

Circuitry for determining the direction of incidence of an acoustic signal in an integrated circuit. An electronic circuit includes a packaged integrated circuit. The packaged integrated circuit includes a die. The die includes a plurality of acoustic transducers spaced apart on the die, and a measurement circuit. The plurality of acoustic transducers includes at least a first acoustic transducer and a second acoustic transducer. The measurement circuit is coupled to at least the first acoustic transducer and the second acoustic transducer. The measurement circuit is configured to determine for the first acoustic transducer, a first time at which the first acoustic transducer detects an acoustic signal propagating in the die; and determine for the second acoustic transducer, a second time at which the second acoustic transducer detects the acoustic signal propagating in the die.

Detection of strain direction in an integrated circuit

In described examples, a ring oscillator includes a series of N stages in a first ring. Each stage includes a respective output terminal coupled to a respective input terminal of a next one of the stages in the first ring. N is a positive odd-numbered integer of at least three. A series of N level shifters in a second ring are respectively connected to the N stages. Each level shifter receives a respective clock output from a respective output terminal of a stage to which it is connected and generates a respective boosted clock output in response thereto. The boosted clock output is coupled to control an impedance state of a next one of the level shifters in the second ring.

Multiphase oscillator circuit

An integrated circuit including a ferroelectric random access memory (FRAM) for storing firmware, and a method of updating that firmware. The FRAM is constructed to selectively operate as a 2T2C FRAM memory in a normal operating mode, and as a 1T1C FRAM memory in an update mode. Updating of the stored firmware is performed by placing the FRAM in its update (1T1C) mode and writing the updated code into alternate rows of the 1T1C half-cells at each of a plurality of memory locations, while the other 1T1C half-cells in the other alternate rows retain the original data. Following verification of the updated contents, the original data in the other half-cells are overwritten with the verified updated data, and the operating mode is changed back to the normal (2T2C) operating mode.

Ferroelectric memory expansion for firmware updates

A motor drive circuit includes a first serializer-deserializer (SER-DES) module that converts first SER-DES input signals into a first SER-DES output serial data stream. The first SER-DES input signals relate to motor control inputs or motor drive power outputs. A second SER-DES module converts a second SER-DES input serial data stream corresponding to the first SER-DES output serial data stream into second SER-DES output signals. The second SER-DES input signals relate to motor drive power outputs or motor control inputs. A serial isolation channel provides a galvanic isolation barrier between the first SER-DES module and the second SER-DES module. The serial isolation channel communicates the first SER-DES output serial data stream across the galvanic isolation barrier to provide the second SER-DES input serial data stream.

Serializer-deserializer for motor drive circuit

An integrated circuit (IC) chip includes a substrate of a piezo-electric material having a first resistivity coefficient associated with a first direction that is longitudinal to a first crystal axis and a second resistivity coefficient associated with a second direction that is transverse to the first crystal axis. The first and second resistivity coefficients have opposite signs. The IC chip also includes a first stress sensing element formed in the substrate and coupled to pass a first current therethrough. The first stress sensing element includes a first resistor aligned such that the major direction of current flow through the first resistor is in the first direction and a second resistor coupled in series with the first resistor and aligned such that the major direction of current flow through the second resistor is in the second direction. A ratio of the resistance of the second resistor to the resistance of the first resistor is equal to a value &#x3b1;, where &#x3b1; is equal to the ratio of the first resistivity coefficient to the second resistivity coefficient.

Device and method for on-chip mechanical stress sensing

Described examples include an integrated circuit including a receive portion to receive an encoded transmission on a line. The receive portion has: a wake mode in which the receiver is capable of receiving the encoded transmission; and a sleep mode in which the receiver is not capable of receiving the encoded transmission. A wakeup controller monitors the line for a wakeup signal and provides a signal to the receive portion to cause the receive portion to enter the wake mode when the wakeup controller receives the wakeup signal.

Signal isolation circuit

A power conversion system includes a maximum load current controller that is operable to limit a load current. For example, in a power conversion system operating in a discontinuous conduction mode (DCM), the maximum load current controller limits the load current by determining an idle period in an active cycle for power switches of the maximum load current controller. The maximum load current controller is optionally operable to approximate values for the time idle period that are substantially equal to theoretically calculated values.

Power converter load current control

A power conversion system includes a power transfer estimator that is operable to provide a determination of the cumulative amount of power transferred through the power supply, without additional sensing elements and at extremely low power levels, and to provide such determinations periodically over potentially long periods of time commensurate with the lifetime of a limited power source such as a battery. In a power conversion system operating in a discontinuous conduction mode (DCM), the power transfer estimator determines the charge transferred during each switching cycle, and the total number of switching cycles, to calculate the cumulative amount of power transferred. The power transfer estimator is optionally operable to calculate a value for the inductance to be used in the determination of the cumulative amount of power transferred through the power supply.

Power transfer estimation

A configurable integrated circuit (IC) includes a substrate having a semiconductor surface that the IC is formed within and thereon. The IC includes a configurable Analog Front End (cAFE) including at least one circuit module or input/output (IO), an analog switch having at least a first substantially gate enclosed Metal Oxide Semiconductor Field Effect Transistor (SGEFET) having a gate stack including a gate on a gate dielectric, a source, and a drain. The drain or source is a substantially gate enclosed (SGE) inner electrode relative to the gate, and the other of the source and the drain is outside the gate. The inner electrode of the first SGEFET is directly coupled to an analog bus. A switch control provides control signals to at least the gate of the first SGEFET for controlling a connectivity between the circuit module and/or the IO and the analog bus.

Configurable analog front ends for circuits with substantially gate enclosed inner electrode MOSFET switch

An electronic device includes a bandgap reference voltage generation stage. The bandgap reference voltage generation stage comprises a device with a PN-junction, a current source feeding a first current during a first period of time and a second higher current during a second period of time through the PN-junction. The bandgap reference voltage is generated from a combination of a first voltage drop across the PN-junction during the first period of time and a second voltage drop across the PN-junction during the second period of time. This bandgap reference voltage is formed using switched capacitors.

Electronic device and method providing a voltage reference

The invention relates to an arrangement comprising a logarithmizing unit and a subtracting unit, wherein the subtracting unit has an output at which a voltage value linearly proportional to the temperature can be tapped off.

Arrangement, use of an arrangement, reference voltage source and method for generating a voltage value linearly proportional to the temperature

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Poing, Germany

Ralf Peter Brederlow