Globalfoundries Inc.

Ralf Otterbach

Markus Lenski

Anthony Mowry

Frank Seliger

Kerstin Ruttloff

Guido Koerner

Martin Mazur

Volker Jaschke

In advanced semiconductor devices, spacer elements may be formed on the basis of a multi-station deposition technique, wherein a certain degree of variability of the various sub-layers of the spacer materials, such as a different thickness, may be applied in order to enhance etch conditions during the subsequent anisotropic etch process. Consequently, spacer elements of improved shape may result in superior deposition conditions when using a stress-inducing dielectric material. Consequently, yield losses due to contact failures in densely packed device areas, such as static RAM areas, may be reduced.

Multi-step deposition of a spacer material for reducing void formation in a dielectric material of a contact level of a semiconductor device

By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.

Dopant profile tuning for MOS devices by adapting a spacer width prior to implantation

When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric cap layers of transistors may have experienced a different process history and may thus require a subsequent adaptation of the final cap layer thickness in one type of the transistors. For this purpose, a hard mask material may be used during a process sequence for forming offset spacer elements in one gate electrode structure while covering another gate electrode structure.

Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterning

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Dresden, Germany

Ralf Otterbach